An ILP formulation for architectural synthesis and application mapping on FPGA-based hybrid multi-processor SOC

Abstract

In this paper, we present an ILP formulation to assist designers to identify the architectural design, binding schema and scheduling algorithm while satisfying physical constraints such as available logic resources, computation time and memory usage used. Directing the solver to optimise for logic usage, execution time, or other parameters allows ease of exploration of the design space. This case study shows how a proposed ILP formulation solves the design exploration problem in the domain of FPGA-based MPSoC design.