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2008 International Conference on Field Programmable Logic and Applications最新文献

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Self-recofigurable embedded systems on Spartan-3 斯巴达-3上的自重构嵌入式系统
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4630011
E. Cantó, F. Fons, Mariano López
{"title":"Self-recofigurable embedded systems on Spartan-3","authors":"E. Cantó, F. Fons, Mariano López","doi":"10.1109/FPL.2008.4630011","DOIUrl":"https://doi.org/10.1109/FPL.2008.4630011","url":null,"abstract":"This paper describes the architecture and design flow of a self-reconfigurable embedded system, mapped on a Spartan-3 low-cost FPGA, where a fixed area is reserved to accommodate a reconfigurable coprocessor. Spartan-3 low-cost family lacks of the ICAP (Internal Configuration Access Port) and design tools for self-reconfiguration. The paper also deals with other issues, such as OPB isolation, bit-stream retrieve from external SRAM, bit-stream processing, and clock routing.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130358230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
SPP1148 booth: Coarse-grained reconfiguration SPP1148展位:粗粒度重构
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629957
Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, W. Rosenstiel, Alexander Thomas, J. Becker, Frank Hannig, D. Kissler, H. Dutta, J. Teich, H. Hinkelmann, P. Zipf, M. Glesner
{"title":"SPP1148 booth: Coarse-grained reconfiguration","authors":"Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, W. Rosenstiel, Alexander Thomas, J. Becker, Frank Hannig, D. Kissler, H. Dutta, J. Teich, H. Hinkelmann, P. Zipf, M. Glesner","doi":"10.1109/FPL.2008.4629957","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629957","url":null,"abstract":"In the last years, aside from fine-grained reconfigurable architectures such as FPGAs, coarse-grained reconfigurable architectures (CGRAs), which typically have building blocks of a fixed bit-width (8 bit, 16 bit, etc.), have gained in importance in academia as well as in industry. CGRAs are usually used for domain-specific computations and have advantages over traditional FPGAs in terms of area and power cost, performance, and reconfiguration time. Thus, architectures with coarse-grained reconfiguration features have also been studied in projects (Sec. 1, 2, 4) within the priority program Reconfigurable Computing Systems and the project CoMap (Sec. 3), which are all sponsored by the German science foundation.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129748487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The hardware application platform of the hartes project harts项目硬件应用平台
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629978
Immacolata Colacicco, G. Marchiori, R. Tripiccione
{"title":"The hardware application platform of the hartes project","authors":"Immacolata Colacicco, G. Marchiori, R. Tripiccione","doi":"10.1109/FPL.2008.4629978","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629978","url":null,"abstract":"We describe the hardware platform that will be used to run several demonstrator applications within the EU-funded hArtes project. hArtes' main goal is to support, with appropriate tools, the development of complex applications on heterogeneous and reconfigurable systems. Our platform provides a number of heterogeneous computing sub-systems, such as DSPs, general-purpose CPUs and configurable elements (in the shape of FPGAs). The envisaged applications are mainly in the audio realm, so support for high-quality audio I/O is also present. FPGAs play a dual role: i) they support I/O functions for audio streaming, moving audio signals from/to main memory with full hardware support; ii) tightly coupled to traditional processors, they make up the reconfigurable processing core within the system. This paper describes the architecture and the first implementation of the platform.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122674357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Customized Reconfigurable Interconnection Networks for multiple application SOCS 定制可重构互联网络的多应用soc
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629991
Hongbing Fan, Jason B. Ernst, Yu-Liang Wu
{"title":"Customized Reconfigurable Interconnection Networks for multiple application SOCS","authors":"Hongbing Fan, Jason B. Ernst, Yu-Liang Wu","doi":"10.1109/FPL.2008.4629991","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629991","url":null,"abstract":"A customized reconfigurable interconnection network (CRIN) refers to a minimal switching network, yielding routing solutions for any element in a pre-given set of routing requirements. The CRIN design problem looks for the best performance and resource-flexibility trade-off between two extreme design contexts ASIC and FPGA. In this paper we give the modeling of this problem for both directed and undirected interconnections. A heuristic algorithm for automatic generation of CRIN is proposed along with its experimental justifications. This study was motivated from the design of reconfigurable systems-on-a-chip for multiple applications.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115839946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Teaching FPGA system design via a remote laboratory facility 通过远程实验室设施设计教学FPGA系统
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4630040
Y. Rajasekhar, William V. Kritikos, A. Schmidt, R. Sass
{"title":"Teaching FPGA system design via a remote laboratory facility","authors":"Y. Rajasekhar, William V. Kritikos, A. Schmidt, R. Sass","doi":"10.1109/FPL.2008.4630040","DOIUrl":"https://doi.org/10.1109/FPL.2008.4630040","url":null,"abstract":"This short paper describes a remote laboratory facility for platform FPGA education. With the addition of an inexpensive piece of hardware, many commercial off-the-shelf FPGA development boards can be made suitable for use in a remote laboratory. The hardware and software required to implement a remote laboratory has been developed and a remote laboratory facility deployed at the University of North Carolina at Charlotte. Advantages, concerns, and actual costs are reported. The experience of using this facility in a senior/first-year graduate-level platform FPGA course is also described. Although these data are preliminary, survey results and first-hand experience with the laboratory were very encouraging and suggests that further studies on student learning are warranted.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127498888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
SPP1148 booth: Hyperreconfigurable architectures SPP1148展位:超可重构架构
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629961
S. Lange, M. Middendorf
{"title":"SPP1148 booth: Hyperreconfigurable architectures","authors":"S. Lange, M. Middendorf","doi":"10.1109/FPL.2008.4629961","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629961","url":null,"abstract":"Dynamically reconfigurable hardware offers promising possibilities for flexible, computation intensive applications. With the technological advance of reconfigurable hardware came a rapid growth in the number of resources per chip requiring large amounts of data transfer per reconfiguration. Especially run-time reconfigurable applications, which make frequent use of reconfiguration, suffer from the growing overhead induced thereby. In this project, we investigate novel concepts for reconfigurable architectures that can dynamically reconfigure the actual reconfiguration potential to reduce the total amount of reconfiguration data that is necessary for a computation.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115939324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Operating system support for online partial dynamic reconfiguration management 操作系统支持在线部分动态重新配置管理
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629982
M. Santambrogio, V. Rana, D. Sciuto
{"title":"Operating system support for online partial dynamic reconfiguration management","authors":"M. Santambrogio, V. Rana, D. Sciuto","doi":"10.1109/FPL.2008.4629982","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629982","url":null,"abstract":"One of the main characteristics of reconfigurable embedded systems is their ability to be dynamically modified to be adapted at run-time to the current environment. This feature, that makes it possible to change the functionality of a system while it is up and running, requires a software application that is able to handle the reconfiguration process. The software for the management of reconfiguration can be developed either as a standalone application, that has to be specifically designed for each given system, or within an operating system, in order to fully exploit both code reuse and code portability. This paper proposes a novel methodology for the design of dynamically reconfigurable systems in which the reconfiguration management is completely assigned to an operating system reconfiguration support. Finally, a prototype implementation is presented, where a standard Linux operating system has been extended with the proposed operating system support in order to handle dynamically reconfigurable hardware resources.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124946274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Low-latency high-bandwidth HW/SW communication in a virtual memory environment 虚拟内存环境下的低延迟高带宽硬件/软件通信
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629945
H. Lange, A. Koch
{"title":"Low-latency high-bandwidth HW/SW communication in a virtual memory environment","authors":"H. Lange, A. Koch","doi":"10.1109/FPL.2008.4629945","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629945","url":null,"abstract":"Adaptive computers combine conventional software programmable processors with reconfigurable compute units. We present techniques that allow the high-performance realization of demand-paged, virtually addressed main memory shared between both of these processing elements. Furthermore, we have achieved low-latency communication between software running on the CPU and the reconfigurable compute unit, allowing even fine-grained hardware/software partitioning. A system-level evaluation quantifies the advantages of our approach.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128855008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Active kernel monitoring to combat scheduler gaming in reconfigurable computing systems 在可重构计算系统中对抗调度程序博弈的主动内核监控
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4630021
Wenyin Fu, Katherine Compton
{"title":"Active kernel monitoring to combat scheduler gaming in reconfigurable computing systems","authors":"Wenyin Fu, Katherine Compton","doi":"10.1109/FPL.2008.4630021","DOIUrl":"https://doi.org/10.1109/FPL.2008.4630021","url":null,"abstract":"Effective reconfigurable hardware (RH) allocation plays a critical role in multi-tasking systems. Past RH scheduling research has focused on how to allocate RH based on the area and performance of competing hardware kernels. However, these approaches generally assume that the metrics associated with those hardware kernels are pre-determined. However, design-time estimates may not always be accurate or even stable. If the scheduler uses incorrect information, performance of one or more applications will suffer. In this paper, we adapt common performance-monitoring techniques to reconfigurable computing and quantify the importance of active performance monitoring of reconfigurable applications.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130120243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power efficient DSP datapath configuration methodology for FPGA FPGA的高能效DSP数据路径配置方法
2008 International Conference on Field Programmable Logic and Applications Pub Date : 2008-09-23 DOI: 10.1109/FPL.2008.4629997
S. McKeown, Roger Francis Woods, J. McAllister
{"title":"Power efficient DSP datapath configuration methodology for FPGA","authors":"S. McKeown, Roger Francis Woods, J. McAllister","doi":"10.1109/FPL.2008.4629997","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629997","url":null,"abstract":"Exploiting the underutilisation of variable-length DSP algorithms during normal operation is vital, when seeking to maximise the achievable functionality of an application within peak power budget. A system level, low power design methodology for FPGA-based, variable length DSP IP cores is presented. Algorithmic commonality is identified and resources mapped with a configurable datapath, to increase achievable functionality. It is applied to a digital receiver application where a 100% increase in operational capacity is achieved in certain modes without significant power or area budget increases. Measured results show resulting architectures requires 19% less peak power, 33% fewer multipliers and 12% fewer slices than existing architectures.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121290673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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