2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS)最新文献_第2页

Modeling for SRAM reliability degradation due to gate oxide breakdown with a compact current model 基于紧凑电流模型的栅极氧化物击穿导致的SRAM可靠性退化建模

2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2017-11-01 DOI: 10.1109/DCIS.2017.8311631

Rui Zhang, Taizhi Liu, Kexin Yang, L. Milor

引用次数: 5

Short and long distance marker detection technique in outdoor and indoor environments for embedded systems 嵌入式系统在室外和室内环境中的短距离和长距离标记检测技术

2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2017-11-01 DOI: 10.1109/DCIS.2017.8311629

Álvaro Díaz, Daniel Peña, E. Villar

{"title":"Short and long distance marker detection technique in outdoor and indoor environments for embedded systems","authors":"Álvaro Díaz, Daniel Peña, E. Villar","doi":"10.1109/DCIS.2017.8311629","DOIUrl":"https://doi.org/10.1109/DCIS.2017.8311629","url":null,"abstract":"During the last years, the market of embedded vision-based systems has been growing at an accelerated rate. Virtual and augmented reality has the potential to become one of the most innovative technologies for the next decade. One of the most important aspects of these technologies is related to the spatial location of objects or people in defined environments, for which there are several techniques. One of the most widely used is based on visual marker recognition. The main problems of these approaches are related to the accuracy, the changing environments, the processing time, the operating range/distance and the price. The popularization of these technologies produces a pull effect toward the companies developing the best technology at the lowest price. This paper proposes a marker design and an algorithm to detect the markers under different ambient conditions, with a long range to be executed on embedded systems with low computational requirements. The proposed method reduces the existing problems in the state-of-the-art related to the use of different environments and conditions such as different distances or different illumination. Moreover, the requisites of the method are minimal to reduce the cost of deployment.","PeriodicalId":136788,"journal":{"name":"2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116795286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Design methodology for power-efficient SC delta-sigma modulators based on switched-VMAs 基于开关式vma的高能效SC δ - σ调制器设计方法

2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2017-11-01 DOI: 10.1109/DCIS.2017.8311644

J. Cisneros-Fernández, L. Terés, M. Dei, F. Serra-Graells

引用次数: 2

SPICE model for the ramp rate effect in the reset characteristic of memristive devices 忆阻器件复位特性中斜坡速率效应的SPICE模型

2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2017-11-01 DOI: 10.1109/DCIS.2017.8311635

A. Rodríguez-Fernandez, J. Suñé, E. Miranda, M. B. González, F. Campabadal, M. M. A. Chawa, R. Picos

引用次数: 4

Break even time analysis using empirical overhead parameters for embedded systems on SOTB technology 基于SOTB技术的嵌入式系统的经验开销参数的盈亏平衡时间分析

2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2017-11-01 DOI: 10.1109/DCIS.2017.8311633

Carlos Cortes, H. Amano, N. Yamasaki

引用次数: 2

Crypto-Test-Lab for security validation of ECC co-processor test infrastructure 用于ECC协处理器测试基础设施安全验证的Crypto-Test-Lab

2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2017-11-01 DOI: 10.1109/DCIS.2017.8311632

E. Lupon, R. Rodríguez-Montañés, S. Manich

{"title":"Crypto-Test-Lab for security validation of ECC co-processor test infrastructure","authors":"E. Lupon, R. Rodríguez-Montañés, S. Manich","doi":"10.1109/DCIS.2017.8311632","DOIUrl":"https://doi.org/10.1109/DCIS.2017.8311632","url":null,"abstract":"Elliptic Curve Cryptography (ECC) is a technology for public-key cryptography that is becoming increasingly popular because it provides greater speed and implementation compactness than other public-key technologies. Calculations, however, may not be executed by software, since it would be so time consuming, thus an ECC co-processor is commonly included to accelerate the speed. Test infrastructure in crypto co-processors is often avoided because it poses serious security holes against adversaries. However, ECC co-processors include complex modules for which only functional test methodologies are unsuitable, because they would take an unacceptably long time during the production test. Therefore, some internal test infrastructure is always included to permit the application of structural test techniques. Designing a secure test infrastructure is quite a complex task that relies on the designer's experience and on trial & error iterations over a series of different types of attacks. Most of the severe attacks cannot be simulated because of the demanding computational effort and the lack of proper attack models. Therefore, prototypes are prepared using FPGAs. In this paper, a Crypto-Test-Lab is presented that includes an ECC co-processor with flexible test infrastructure. Its purpose is to facilitate the design and validation of secure strategies for testing in this type of co-processor.","PeriodicalId":136788,"journal":{"name":"2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131407628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Full-3D printed electronics process using stereolitography and electroless plating 全3d打印电子工艺使用立体光刻和化学镀

2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2017-11-01 DOI: 10.1109/DCIS.2017.8311624

A. Salas-Barenys, N. Vidal, J. Sieiro, J. López-Villegas, B. Medina-Rodriguez, F. Ramos

引用次数: 7

Merging smart wearable devices and wireless mesh networks for collaborative sensing 融合智能可穿戴设备和无线网状网络进行协同传感

2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2017-11-01 DOI: 10.1109/DCIS.2017.8311637

Jaime Zornoza, Gabriel Mujica, J. Portilla, T. Riesgo

引用次数: 9

CCO-based analog front-end for iStents 基于cco的iStents模拟前端

2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2017-11-01 DOI: 10.1109/DCIS.2017.8311643

J. Miguel, Y. Lechuga, M. A. Allende, M. Martinez

引用次数: 1

Bulk-based DC offset calibration for low-power memristor array read-out system 小功率忆阻阵列读出系统的大体积直流偏置校正

2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS) Pub Date : 2017-11-01 DOI: 10.1109/DCIS.2017.8311626

C. Mohan, L. Camuñas-Mesa, E. Vianello, L. Perniola, C. Reita, J. M. de la Rosa, T. Serrano-Gotarredona, B. Linares-Barranco

{"title":"Bulk-based DC offset calibration for low-power memristor array read-out system","authors":"C. Mohan, L. Camuñas-Mesa, E. Vianello, L. Perniola, C. Reita, J. M. de la Rosa, T. Serrano-Gotarredona, B. Linares-Barranco","doi":"10.1109/DCIS.2017.8311626","DOIUrl":"https://doi.org/10.1109/DCIS.2017.8311626","url":null,"abstract":"Memristors in neuromorphic circuits typically need to drive currents of many mA because their Low Resistance State (LRS) is in the order of a few kΩ and many devices need to be activated simultaneously which results in high power consumptions. Reducing read-out pulses amplitudes below the typical 0.1V is not trivial, as offset voltages of read-out circuits start to affect the results. This paper presents a three-stage cascaded calibration to compensate for the resting offset voltage of crossbar lines generated in the amplifiers driving memristive devices in memristor array read-out systems. The proposed calibration technique is based on adjusting the bulk voltage of the input differential pairs by means of a switchable cascade of resistor ladders. As a result, the calibrated offset voltage can be further reduced with the number of stages in the cascade, leading to a calibration voltage step below 0.1mV — only limited in practice by mismatch and electrical noise. The circuit has been designed in 130nm CMOS technology, and its operation has been verified with oxide-based resistive memory (OxRAM) devices operated in binary mode to implement synapses in neuro-morphic circuits. Layout-extracted simulations considering PVT variations are considered to validate the presented calibration technique.","PeriodicalId":136788,"journal":{"name":"2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115035562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0