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System-in-Package Matching Network for RF Wireless Transceivers 用于射频无线收发器的系统级包匹配网络
2016 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2016-10-01 DOI: 10.1109/AUSTROCHIP.2016.018
Graciele Batistell, Timo Holzmann, H. Sterner, J. Sturm
{"title":"System-in-Package Matching Network for RF Wireless Transceivers","authors":"Graciele Batistell, Timo Holzmann, H. Sterner, J. Sturm","doi":"10.1109/AUSTROCHIP.2016.018","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2016.018","url":null,"abstract":"The experimental and simulative investigation, as well as measurement results of an on-package planar transformers is presented. The proposed transformer is designed as part of an impedance matching network for a center frequency of 750 MHz. The transformer is designed using FEM simulators and produced on a 3-layer core-less package technology. The transformer inductors reach Q-factors between 25 and 35, and coupling factor around 0.6. Simulations and measurement results present a good agreement and show that the use of on-package transformers is a promising alternative for the currently standard integrated transformers.","PeriodicalId":134390,"journal":{"name":"2016 Austrochip Workshop on Microelectronics (Austrochip)","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124622723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High-Efficiency CMOS Buck Converter with Wide Output Voltage Range 宽输出电压范围的高效CMOS降压变换器
2016 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2016-10-01 DOI: 10.1109/AUSTROCHIP.2016.014
N. Mitrovic, R. Enne, H. Zimmermann
{"title":"High-Efficiency CMOS Buck Converter with Wide Output Voltage Range","authors":"N. Mitrovic, R. Enne, H. Zimmermann","doi":"10.1109/AUSTROCHIP.2016.014","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2016.014","url":null,"abstract":"This paper presents an integrated DC-DC buck converter with variable output voltage (from 1.2 V up to 5 V) and capability for delivering a wide range of output currents. The converter is optimized for achieving high efficiency, which is in range from 88% to 94.4% for output voltages from 1.2 V to 3.1V and output currents from 0.4 A to 1.2 A. Also, an overview of the converter losses is given, especially considering the losses caused by the high-side (HS) and low-side (LS) switching transistors.","PeriodicalId":134390,"journal":{"name":"2016 Austrochip Workshop on Microelectronics (Austrochip)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133112131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Capacitance-to-Digital Converter Based on a Ring Oscillator with Flicker Noise Reduction 一种基于消闪噪声环振的电容-数字转换器
2016 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2016-10-01 DOI: 10.1109/AUSTROCHIP.2016.019
Andrés Quintero, Fernando Cardes, L. Hernández, C. Buffa, A. Wiesbauer
{"title":"A Capacitance-to-Digital Converter Based on a Ring Oscillator with Flicker Noise Reduction","authors":"Andrés Quintero, Fernando Cardes, L. Hernández, C. Buffa, A. Wiesbauer","doi":"10.1109/AUSTROCHIP.2016.019","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2016.019","url":null,"abstract":"This paper presents a ring oscillator based readoutcircuit for differential capacitive MEMS. Flicker noise isreduced by modulating it to frequencies above the bandwidthof interest and then filtering. A technique equivalent tochopping in conventional switched capacitor circuits isdeveloped and applied to a single ended ring oscillatorcontrolled by the MEMS capacitance. A prototype wasdesigned in a 0.12 um CMOS process. Simulations show thatflicker noise is attenuated and Signal-to-Noise Ratio isimproved.","PeriodicalId":134390,"journal":{"name":"2016 Austrochip Workshop on Microelectronics (Austrochip)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134203671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Programmable Delay Line for Metastability Characterization in FPGAs fpga亚稳态特性的可编程延迟线
2016 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2016-10-01 DOI: 10.1109/AUSTROCHIP.2016.021
T. Polzer, F. Huemer, A. Steininger
{"title":"A Programmable Delay Line for Metastability Characterization in FPGAs","authors":"T. Polzer, F. Huemer, A. Steininger","doi":"10.1109/AUSTROCHIP.2016.021","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2016.021","url":null,"abstract":"The experimental metastability characterizationof a flip flop requires a controllable delay with low jitter andhigh time resolution. In FPGAs such an experiment can bevery useful for in-situ or even online characterization of agiven flip flop, but existing solutions rely on the availability ofa digital clock manager (DCM) or a phase locked loop (PLL) for implementing this controllable delay. Given that such acomponent may not always be available, and that its linearityis sometimes sub-optimal and hard to calibrate, we present analternative approach in this paper. It is based on the use ofthe carry chain for determining the delay steps, which allows avery fine resolution. For calibration of the step sizes we proposeto operate the delay line in a ring oscillator whose frequencyis then measured for all delay settings. Our results show thatthis solution yields a fine-grain delay control with acceptablejitter. We demonstrate the usefulness of our approach in thecontext of a complete metastability characterization that nowcan be performed without requiring a DCM or PLL.","PeriodicalId":134390,"journal":{"name":"2016 Austrochip Workshop on Microelectronics (Austrochip)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114350765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Threshold Voltage Compensated RF-DC Power Converters in a 40 nm CMOS Technology 阈值电压补偿的40nm CMOS RF-DC功率变换器
2016 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2016-10-01 DOI: 10.1109/AUSTROCHIP.2016.017
L. Zöscher, Peter Herkess, J. Grosinger, U. Muehlmann, Dominik Amschl, H. Watzinger, W. Bösch
{"title":"Threshold Voltage Compensated RF-DC Power Converters in a 40 nm CMOS Technology","authors":"L. Zöscher, Peter Herkess, J. Grosinger, U. Muehlmann, Dominik Amschl, H. Watzinger, W. Bösch","doi":"10.1109/AUSTROCHIP.2016.017","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2016.017","url":null,"abstract":"Circuit techniques termed as threshold voltage (Vth) compensation are utilized for CMOS RF-DC power converters or more specifically RF charge pumps to improve the power conversion efficiency at low levels of RF input voltage. In this work, we present two differential RF charge pumps for UHF RFID transponder ICs that include a Vth compensation. The first circuit uses gate biasing for Vth compensation, whereas the second circuit design follows a combined approach of gate and bulk biasing. The circuits have been manufactured in a 40nm low-power CMOS technology. Measurement results demonstrate that the power conversion efficiency can be improved from 39% to 42% at a given output power of 4µW and an output voltage of 1V by using bulk biasing. Both circuits show a low input quality factor of 13 at this output power level and allow therefore the implementation of highly sensitive broadband UHF RFID transponders.","PeriodicalId":134390,"journal":{"name":"2016 Austrochip Workshop on Microelectronics (Austrochip)","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134431986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Modeling and Simulation of Digital Control Schemes for Two-Phase Interleaved Buck Converters 两相交错降压变换器数字控制方案的建模与仿真
2016 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2016-10-01 DOI: 10.1109/AUSTROCHIP.2016.013
Marc Kanzian, M. Agostinelli, M. Huemer
{"title":"Modeling and Simulation of Digital Control Schemes for Two-Phase Interleaved Buck Converters","authors":"Marc Kanzian, M. Agostinelli, M. Huemer","doi":"10.1109/AUSTROCHIP.2016.013","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2016.013","url":null,"abstract":"The importance of energy-efficient DC voltage conversionis ever increasing. This demands for advanced topologiessuch as time-interleaved multiphase DC-DC converters. Anessential part of such a converter is the control loop, which not only regulates the output voltage, but also balances the currents of the individual phases. In this paper, a small-signal model of a two-phase buck converter is derived, and a linear voltage-mode controller is presented. Further, a current balancing scheme that only requires input current sensing is investigated. Finally, the benefits of a multisampled controller and digital pulse width modulator are highlighted.","PeriodicalId":134390,"journal":{"name":"2016 Austrochip Workshop on Microelectronics (Austrochip)","volume":"25 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130351107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 11-Bit Integrating Analog to Digital Converter 一种11位集成模数转换器
2016 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2016-10-01 DOI: 10.1109/AUSTROCHIP.2016.015
Darshan Shetty, P. Renukaswamy
{"title":"A 11-Bit Integrating Analog to Digital Converter","authors":"Darshan Shetty, P. Renukaswamy","doi":"10.1109/AUSTROCHIP.2016.015","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2016.015","url":null,"abstract":"This paper describes an integrating analog to digital converter (iADC) based on the dual slope principle. This circuit was designed, fabricated and evaluated in course of a student project in the master degree program ISCD - Integrated Systems and Circuits Design of Carinthia University of Applied Sciences. The mixed-signal circuit consists of the analog front end with integrator and comparator stages, switches as well as current references and a digital control part, fabricated in a 0.35 um CMOS technology. A novel common mode control technique has been implemented for the integrating amplifier and filter caps are added to improve the overall iADC performance. Measurements on fabricated samples show that, with a 997 Hz input, the iADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.94 dB, spurious-free dynamic range (SFDR) of 49.53 dB, effective number of bits (ENOB) of 8 bit, peak integral non-linearity (INL) of 0.6/-5.8 LSB and peak differential nonlinearity (DNL) of 6.5/-1 LSB. The active area of the iADC is 620 µm × 148 µm, and the power dissipation is 19.8 mW from a 3.3 V supply.","PeriodicalId":134390,"journal":{"name":"2016 Austrochip Workshop on Microelectronics (Austrochip)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127020910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis and Design of Differential Feedback CG LNA Topologies for Low Voltage Multistandard Wireless Receivers 低压多标准无线接收机差分反馈CG LNA拓扑分析与设计
2016 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2016-10-01 DOI: 10.1109/AUSTROCHIP.2016.016
P. Renukaswamy, V. Pasupureddi, J. Sturm
{"title":"Analysis and Design of Differential Feedback CG LNA Topologies for Low Voltage Multistandard Wireless Receivers","authors":"P. Renukaswamy, V. Pasupureddi, J. Sturm","doi":"10.1109/AUSTROCHIP.2016.016","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2016.016","url":null,"abstract":"This work presents the design and analysis of differential feedback common gate (CG) Low Noise Amplifier (LNA) topologies for low voltage multistandard operation. The qualitative and quantitative analysis presented in this paper establishes that the optimum gain (S21), low Noise Figure (NF) and improved linearity can be achieved in a differential CG LNA using negative cross-coupled feedback compared to the common belief that a positive-negative feedback is superior. The positive-negative feedback CG LNA increases S21 but not necessarily improves the NF and linearity, especially for low supply voltage multistandard RF receiver frontends. This is dueto the reduced supply voltage and profound increase of other second order effects in sub-100 nm CMOS technologies, leading to difficulties in the design of multistandard receivers where CG LNA with resistive load is needed. To prove the analysis presented in this paper, a 1.2 V, 65 nm CMOS differential negative feedback capacitor cross-coupled LNA is designed. The schematic simulation results of the implemented differential capacitor cross-coupled CG LNA in 65 nm CMOS achieves maximum S21 of 18.03 dB, minimum NF of 2.25 dB, input referred third order intercept point (IIP3) at maximum S21 of -3.76 dBm and 5.17 mW of power consumption with input matching (S11).","PeriodicalId":134390,"journal":{"name":"2016 Austrochip Workshop on Microelectronics (Austrochip)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128293891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Advanced Pseudo Differential Amplifier with Output Common Mode Regulation and Phase Shift Retention 具有输出共模调节和相移保持的先进伪差分放大器
2016 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2016-10-01 DOI: 10.1109/AUSTROCHIP.2016.012
Sagarika Donepudi, Michael Köberle, W. Horn
{"title":"Advanced Pseudo Differential Amplifier with Output Common Mode Regulation and Phase Shift Retention","authors":"Sagarika Donepudi, Michael Köberle, W. Horn","doi":"10.1109/AUSTROCHIP.2016.012","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2016.012","url":null,"abstract":"In the past decades, the use of sensors in the automotive sector has evolved exponentially. The Anti-Lock Brakingsystem (ABS) has been improved considerably. These systemsuse magnetic sensors (Giant Magneto Resistance (GMR)) witha pole toothed wheel to generate a signal. Currently there areused two preamplifiers to process the information from theGMR bridge to detect speed and direction. In the new ABSsensor architecture, both amplitude and phase information canbe processed simultaneously by a single pre-amplifier to detectspeed and direction. The goal is to develop a part of that system, a pseudo differential amplifier to be integrated on chip usingBiCMOS technology. It amplifies the signal received from anew GMR transducer bridge in the ABS. This paper addressesthe design of a new implementation of preamplifier \"AdvancedPseudo Differential Amplifier (PDA)\" by maintaining the phaseshift and the common mode of the GMR transducer output. This\"Advanced PDA\" must conform to tight design specifications, such as an output common mode of 1:25 V ±10 %, an inputreferred noise of 5 µV/√Hz, a gain of 11 ±5 %, an attenuation@ 3 kHz of +2 %, a linearity of 97 % (@ an input signal amplitude of ±100 mV), and finally differential phase variationsof 10° (input vs output) for implementation in ABS systems.","PeriodicalId":134390,"journal":{"name":"2016 Austrochip Workshop on Microelectronics (Austrochip)","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122980301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An EMI Receiver Model to Minimize Simulation Time of Long Data Transmissions 最小化长数据传输仿真时间的电磁干扰接收机模型
2016 Austrochip Workshop on Microelectronics (Austrochip) Pub Date : 2016-10-01 DOI: 10.1109/AUSTROCHIP.2016.022
H. Hackl, B. Deutschmann
{"title":"An EMI Receiver Model to Minimize Simulation Time of Long Data Transmissions","authors":"H. Hackl, B. Deutschmann","doi":"10.1109/AUSTROCHIP.2016.022","DOIUrl":"https://doi.org/10.1109/AUSTROCHIP.2016.022","url":null,"abstract":"For evaluating the electromagnetic emission (EME) of an integrated circuit (IC) during the design phase, a precise transient simulation of the disturbing signal is required. This usually takes a lot of time, so that simulating a signal trace longer than a couple of ms is not feasible. In this paper an extension to an existing electromagnetic interference (EMI) receiver model is introduced, which enables to interpolate the emission spectrum of very long transient data with repetitive contents (like digital data transmissions) while using only short parts of the overall signal as input. Therewith the IC simulation time can be reduced by far without losing accuracy in the EME post-processing stage.","PeriodicalId":134390,"journal":{"name":"2016 Austrochip Workshop on Microelectronics (Austrochip)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123631904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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