A Programmable Delay Line for Metastability Characterization in FPGAs

Abstract

The experimental metastability characterizationof a flip flop requires a controllable delay with low jitter andhigh time resolution. In FPGAs such an experiment can bevery useful for in-situ or even online characterization of agiven flip flop, but existing solutions rely on the availability ofa digital clock manager (DCM) or a phase locked loop (PLL) for implementing this controllable delay. Given that such acomponent may not always be available, and that its linearityis sometimes sub-optimal and hard to calibrate, we present analternative approach in this paper. It is based on the use ofthe carry chain for determining the delay steps, which allows avery fine resolution. For calibration of the step sizes we proposeto operate the delay line in a ring oscillator whose frequencyis then measured for all delay settings. Our results show thatthis solution yields a fine-grain delay control with acceptablejitter. We demonstrate the usefulness of our approach in thecontext of a complete metastability characterization that nowcan be performed without requiring a DCM or PLL.