Analysis and Design of Differential Feedback CG LNA Topologies for Low Voltage Multistandard Wireless Receivers

This work presents the design and analysis of differential feedback common gate (CG) Low Noise Amplifier (LNA) topologies for low voltage multistandard operation. The qualitative and quantitative analysis presented in this paper establishes that the optimum gain (S21), low Noise Figure (NF) and improved linearity can be achieved in a differential CG LNA using negative cross-coupled feedback compared to the common belief that a positive-negative feedback is superior. The positive-negative feedback CG LNA increases S21 but not necessarily improves the NF and linearity, especially for low supply voltage multistandard RF receiver frontends. This is dueto the reduced supply voltage and profound increase of other second order effects in sub-100 nm CMOS technologies, leading to difficulties in the design of multistandard receivers where CG LNA with resistive load is needed. To prove the analysis presented in this paper, a 1.2 V, 65 nm CMOS differential negative feedback capacitor cross-coupled LNA is designed. The schematic simulation results of the implemented differential capacitor cross-coupled CG LNA in 65 nm CMOS achieves maximum S21 of 18.03 dB, minimum NF of 2.25 dB, input referred third order intercept point (IIP3) at maximum S21 of -3.76 dBm and 5.17 mW of power consumption with input matching (S11).