ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)最新文献_第5页

A cell selection algorithm for area minimization 区域最小化的单元格选择算法

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820810

Tae hoon Kim, Young Hwan Kim

引用次数: 0

A study on soft- and hard-breakdowns in MOS capacitors using the parallel stressing method 用平行应力法研究MOS电容器的软击穿和硬击穿

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820872

J. Sim, I. Nam, Sung I. Hong, Jong-Duk Lee, Byung-Gook Park

引用次数: 0

Automatic software toolkit generation for embedded systems-on-chip 嵌入式片上系统的自动软件工具箱生成

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820839

A. Halambi, P. Grun, H. Tomiyama, N. Dutt, A. Nicolau

{"title":"Automatic software toolkit generation for embedded systems-on-chip","authors":"A. Halambi, P. Grun, H. Tomiyama, N. Dutt, A. Nicolau","doi":"10.1109/ICVC.1999.820839","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820839","url":null,"abstract":"Modern embedded Systems-on-Chips (SOCs) will allow the system designer to customize Intellectual Property (IP) cores (fixed and programmable), together with custom logic and large amounts of embedded memory. As the software content in these emerging embedded SOCs begins to dominate the SOC design process, there is a critical need for support of an integrated software development environment (including compilers, simulators and debuggers). Furthermore, since many characteristics of these processor core IPs (e.g., instruction-sets, memory configurations) are increasingly customizable, the entire software toolkit chain needs to be customized and generated to support both early design space exploration (for performance, power and cost constraints), as well as high-qualify software generation. This paper first surveys recent efforts in Architecture Description Languages (ADLs) used to perform early validation and exploration of SOC architectures. The second part of the paper focuses on approaches to software toolkit generation that automatically produce the software infrastructure (e.g., compilers, simulators, debuggers) which will enable true hardware/software codesign of these emerging embedded SOCs.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"65 1","pages":"107-116"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76040670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Growth of RuO/sub x/ thin films by metalorganic chemical vapor deposition 金属有机化学气相沉积法制备RuO/ subx /薄膜

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820985

Younsoo Kim, Kyung-Cheol Jeong, J. Joo, Jongee Park, Jun-Sik Lee, Jong-Woo Yoon, J. Roh

引用次数: 0

Scalable threshold voltage model for deep-submicrometer MOSFET 深亚微米MOSFET的可扩展阈值电压模型

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820990

J. Kahng, J.H. Kim, M. Jo, H. Yoon

引用次数: 1

A 1.25-GBaud CMOS transceiver with on-chip terminator and voltage mode driver for Gigabit Ethernet 1000Base-X 一个1.25 gbaud的CMOS收发器，带有片上终止器和电压模式驱动器，用于千兆以太网1000Base-X

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820937

Gijung Ahn, D. Jeong

引用次数: 0

Self-timed shared division and square-root implementation using full redundant signed digit numbers 使用完全冗余有符号数字的自定时共享除法和平方根实现

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820995

Young-Sang Lee, Jun-Woo Kang, L. Kim, Seung-Ho Hwang

引用次数: 1

DRAM technology: outlook and challenges DRAM技术:展望与挑战

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820868

J. Comfort

{"title":"DRAM technology: outlook and challenges","authors":"J. Comfort","doi":"10.1109/ICVC.1999.820868","DOIUrl":"https://doi.org/10.1109/ICVC.1999.820868","url":null,"abstract":"As we approach the new millenium DRAM technology is faced with a number of significant new challenges in addition to those associated with the historical DRAM scaling paradigm. Continued lithographic capability scaling is of course required, but this must now be accomplished on an accelerated schedule at a time when the overall development infrastructure (masks, inspection, repair, steppers, resists) is struggling to keep up with historical trends. Similar limitations exist for continued scaling of many cell technologies: node dielectric thickness, array transistor threshold/leakage control, support transistor performance, high aspect ratio metallization and gap fill all face fundamental materials or physics limitations which require significant effort and cost to overcome. At the same time. Continued scaling in support of the historical 27%/bit/yr cost decline requires breakthroughs in both cell technology and product architecture to address the theoretical cell area limit of 8 lithographic squares for the classical folded bitline architecture. Finally, these challenges are appearing at a time when the DRAM marketplace is diverging into multiple high performance interface requirements which stress these technology features even further while market pricing continues to put extreme pressure on process and development cost containment. The author reviews many of these challenges, comments on the details of the technical issues and then outlines some alternatives which may address the concerns.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"113 1","pages":"182-186"},"PeriodicalIF":0.0,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85914626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Effects of N/sub 2/ addition on aluminum alloy etching: optical emission spectroscopy studies N/ sub2 /加入对铝合金蚀刻的影响:光学发射光谱研究

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820961

Kil-Ho Kim, K. S. Shin, K. Baek, Chang Wook Park, W. Lee

引用次数: 0

A folded bit-line architecture for high speed CMOS SRAM 高速CMOS SRAM的折叠位线架构

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) Pub Date : 1999-10-26 DOI: 10.1109/ICVC.1999.820998

Sejun Kim, I. Chang, S. Seo, K. Kwack

引用次数: 0