Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping最新文献_第2页

An efficient hierarchical router for large 3D NoCs 一种用于大型3D网络的高效分层路由器

Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping Pub Date : 2010-06-08 DOI: 10.1109/RSP.2010.5656418

W. Lafi, D. Lattard, A. Jerraya

引用次数: 15

An FPGA based semi-parallel architecture for higher order Moving Target Indication (MTI) processing 基于FPGA的高阶运动目标指示(MTI)处理半并行结构

Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping Pub Date : 2010-06-08 DOI: 10.1109/RSP.2010.5656326

Zulfiqar Ali, A. Arshad, U. Razzaq

{"title":"An FPGA based semi-parallel architecture for higher order Moving Target Indication (MTI) processing","authors":"Zulfiqar Ali, A. Arshad, U. Razzaq","doi":"10.1109/RSP.2010.5656326","DOIUrl":"https://doi.org/10.1109/RSP.2010.5656326","url":null,"abstract":"The design and implementation of a higher order Moving Target Indication (MTI) engine is presented. This is part of a single chip radar signal processor also incorporating the subsequent algorithms. The bottleneck in use of higher order filters for MTI is not an algorithmic one but one related to implementation. Thus the challenge is to minimize area utilization and achieve the required speed. The proposed architecture employs the use of multiple offchip memory banks for achieving the required memory bandwidth and use of dedicated FPGA resources for area minimization. The requirement of stacking a large number of radar returns in memory and then reading them all for filtering within a single return time demands a parallel memory reading and data processing approach. But this demand has to be balanced with the requirement to consume as little area as possible to leave room for the following algorithms. Considering these constraints, a semi parallel architecture employing multiple filters, each built around a DSP48 slice configured as a Multiply Accumulate (MACC) unit in a time shared manner is used. An analysis of various factors that affect speed and area is also made. The architecture is implemented on a Virtex-4SX35 FPGA using Xilinx XtremeDSP Kit. The design is tested using unprocessed baseband data from a TA-10K air traffic control radar. Results show a marked improvement in the clutter suppression capability of the radar. The design achieves the required speed using only 7% of the available FPGA slices. Thus, not only can the other algorithms be implemented on the same chip but there is room for enhancements as well.","PeriodicalId":133782,"journal":{"name":"Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121201154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Automatic modulation classification for rapid radio deployment 用于快速无线电部署的自动调制分类

Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping Pub Date : 2010-06-08 DOI: 10.1109/rsp_2010.46

A. Recio, J. Surís, P. Athanas

引用次数: 2

Performance-cost analyses software for H.264 Forward/Inverse Integer Transform H.264正/逆整数变换性能成本分析软件

Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping Pub Date : 2010-06-08 DOI: 10.1109/RSP.2010.5656347

T. Do, T. M. Le, Binh P. Nguyen, Yajun Ha

{"title":"Performance-cost analyses software for H.264 Forward/Inverse Integer Transform","authors":"T. Do, T. M. Le, Binh P. Nguyen, Yajun Ha","doi":"10.1109/RSP.2010.5656347","DOIUrl":"https://doi.org/10.1109/RSP.2010.5656347","url":null,"abstract":"In the literature, Data Throughput rate per Unit Area (DTUA) has been used as the sole metric to evaluate the effectiveness of H.264 Forward/Inverse Integer Transform (FIT/IIT) designs. However, other than throughput and circuit area involved in DTUA, interconnection, power and delay are not considered. In this paper, we first summarize the Performance-Cost Metric (PCM) technique, where PCM is defined as the ratio of data throughput over the design cost including power, area, delay, and issues associated with interconnections in sub-micron designs. Compared to DTUA, PCM facilitates more comprehensive comparisons for VLSI designs, including FIT/IIT. The contribution of this paper is the software that helps facilitate the use of the PCM technique. When using this software, users are asked to enter some preliminary parameters of their design. Based on the given parameters and the reference designs managed using the software, it then analyzes and provides the possible boundaries of the users' design in order to have better PCMs compared to the reference designs. In addition, it can also export comparison results among different designs. The software is flexibly designed in order to facilitate the use of not only our PCM technique in FIT/IIT designs, but also different metrics in other architectures.","PeriodicalId":133782,"journal":{"name":"Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128450518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Validating quality attribute requirements via execution-based model checking 通过基于执行的模型检查验证质量属性需求

Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping Pub Date : 2010-06-08 DOI: 10.1109/RSP.2010.5656438

D. Drusinsky, M. Shing

引用次数: 6

Failure mode and effect analysis based on electric and electronic architectures of vehicles to support the safety lifecycle ISO/DIS 26262 基于车辆电气和电子架构的故障模式和影响分析，以支持安全生命周期ISO/DIS 26262

Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping Pub Date : 2010-06-08 DOI: 10.1109/RSP.2010.5656351

Martin Hillenbrand, M. Heinz, N. Adler, J. Matheis, K. Müller-Glaser

{"title":"Failure mode and effect analysis based on electric and electronic architectures of vehicles to support the safety lifecycle ISO/DIS 26262","authors":"Martin Hillenbrand, M. Heinz, N. Adler, J. Matheis, K. Müller-Glaser","doi":"10.1109/RSP.2010.5656351","DOIUrl":"https://doi.org/10.1109/RSP.2010.5656351","url":null,"abstract":"The draft international standard under development ISO 26262 (Road Vehicles — Functional safety —) describes a safety lifecycle for road vehicles and thereby influences all parts of development, production, operation and decommissioning. Starting from 2011, all developments of new cars should be aligned to this standard. The rapid application and adaption of the ISO 26262 is mandatory to develop safe, advanced and competitive automotive systems and systems of systems. The failure mode and effect analysis (FMEA) is a well applied engineering quality method in the automotive industry and proposed by the ISO 26262 for several analyses. The communication structure of the automotive control system are specified by the electric and electronic architecture (EEA). For a short time all this information can be processed in one tool. It can form an important contribution to the determination of input data for safety assessments. With the FMEA flow embedded in the EEA modeling, analysis can be rapidly provided with altered input data resulting from architecture modifications. This paper presents a formalized tool flow for rapid determination and accumulation of input data for failure mode and effect analysis based on an EEA model, the accomplishment of the analysis within an EEA modeling tool and the automated generation of reports, documenting the results from the FMEA according to a predefined form.","PeriodicalId":133782,"journal":{"name":"Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116312141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 35

Combining memory optimization with mapping of multimedia applications for multi-processors system-on-chip 将内存优化与多处理器片上系统的多媒体应用映射相结合

Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping Pub Date : 2010-06-08 DOI: 10.1109/RSP.2010.5656435

B. Girodias, Luiza Gheorghe Iugan, Y. Bouchebaba, G. Nicolescu, E. Aboulhamid, M. Langevin, P. Paulin

引用次数: 2

MpAssign: A framework for solving the many-core platform mapping problem MpAssign:用于解决多核平台映射问题的框架

Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping Pub Date : 2010-06-08 DOI: 10.1002/spe.1157

Y. Bouchebaba, A. Özcan, P. Paulin, G. Nicolescu

{"title":"MpAssign: A framework for solving the many-core platform mapping problem","authors":"Y. Bouchebaba, A. Özcan, P. Paulin, G. Nicolescu","doi":"10.1002/spe.1157","DOIUrl":"https://doi.org/10.1002/spe.1157","url":null,"abstract":"Many-core platforms, providing large numbers of parallel execution resources, emerge as a response to the increasing computation needs of embedded applications. A major challenge raised by this trend is the efficient mapping of applications on parallel resources. This is a nontrivial problem because of the number of parameters to be considered for characterizing both the applications and the underlying platform architectures. Recently, several authors have proposed to use Multi-Objective Evolutionary Algorithm (MOEA) to solve this problem within the context of mapping applications on Network-on-Chips (NoC). However, these proposals have several limitations: (1) only few meta-heuristics are explored (mainly NSGAII and SPEA2), (2) only few cost functions are provided, and (3) they only deal with a small number of the application and architecture constraints. In this paper, we propose a new framework which avoids all of the problems cited above. Our framework allows designers to (1) explore several new meta-heuristics, (2) easily add a new cost function (or to use an existing one) and (3) take into account any number of architecture and application constraints. The paper also presents experiments illustrating how our framework is applied to the problem of mapping streaming applications on a NoC based many-core platform.","PeriodicalId":133782,"journal":{"name":"Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130207779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Rapid prototyping and compact testing of CPU emulators 快速原型和紧凑的测试CPU模拟器

Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping Pub Date : 2010-06-08 DOI: 10.1109/RSP.2010.5656339

Weiqin Ma, A. Forin, Jyh-Charn S. Liu

引用次数: 9

Performance evaluation for passive-type Optical network-on-chip 无源型片上光网络的性能评价

Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping Pub Date : 2010-06-08 DOI: 10.1109/RSP.2010.5656333

Atef Allam, I. O’Connor, W. Heirman

{"title":"Performance evaluation for passive-type Optical network-on-chip","authors":"Atef Allam, I. O’Connor, W. Heirman","doi":"10.1109/RSP.2010.5656333","DOIUrl":"https://doi.org/10.1109/RSP.2010.5656333","url":null,"abstract":"Optical networks-on-chip (ONoCs) represent an emerging technology for use as a communication platform for systems-on-chip (SoC). It is a novel on-chip communication system where information is transmitted in the form of light, as opposed to the conventional electrical network-on-chip (ENoC). This work studies the performance of a class of ONoCs that employ a single central passive-type optical router using wavelength division multiplexing (WDM) as a routing mechanism. The ONoC performance analysis has been carried out both at system-level (network latency and throughput) and at the physical level. In physical-level (optical) performance analysis of the ONoC, we study the communication reliability of the ONoC formulated by the signal-to-noise ratio (SNR) and the bit error rate (BER). Optical performance of the ONoC is carried out based on the system parameters, component characteristics and technology. The system-level analysis is carried out through simulation using flit-level-accurate SystemC model. Experimental results prove the scalability of the ONoC and demonstrate that the ONoC is able to deliver a comparable bandwidth or even better (in large network sizes) to the ENoC.","PeriodicalId":133782,"journal":{"name":"Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132302103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3