Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping最新文献_第3页

Counter Embedded Memory architecture for trusted computing platform 可信计算平台的计数器嵌入式存储器体系结构

Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping Pub Date : 2010-06-08 DOI: 10.1109/RSP.2010.5656329

Gavin Xiaoxu Yao, R. Cheung, K. Man

{"title":"Counter Embedded Memory architecture for trusted computing platform","authors":"Gavin Xiaoxu Yao, R. Cheung, K. Man","doi":"10.1109/RSP.2010.5656329","DOIUrl":"https://doi.org/10.1109/RSP.2010.5656329","url":null,"abstract":"Due to various hacker attacks, trusted computing platform has received a lot of attentions recently. Encryption is introduced to maintain the confidentiality of data stored on such platform, while Message Authentication Codes (MACs) and authentication trees are employed to verify the data memory integrity. These encryption and authentication architectures suffer from several potential vulnerabilities which have been omitted by the previous work. In this paper, we first address our concern about a type of cryptanalysis; a ciphertext stored on memory can be decrypted and attacked by an adversary and the MACs and the authentication trees would become the victim of cryptanalytic attacks. In addition, we show that such an attack can be extended to multi-core systems by simply corrupting other unprotected cores and performing malicious behaviors. To handle these scenarios, we propose a Counter Embedded Memory (CEM) design, and employ embedded counters to record every data fetch and trace malicious operations. The proposed platform with CEM allows the system to trace unexpected memory access, thus can indicate potential attack in progress. We present both qualitative discussion and quantitative analysis to show the effectiveness of the proposed architecture. Our FPGA rapid prototype shows that the additional memory overhead is only 0.10% and the latency can be totally neglected.","PeriodicalId":133782,"journal":{"name":"Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131152636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Host-compiled simulation of multi-core platforms 多核平台主机编译仿真

Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping Pub Date : 2010-06-08 DOI: 10.1109/RSP.2010.5656352

A. Gerstlauer

引用次数: 25

Rapid specification of hardware-in-the-loop test systems in the automotive domain based on the electric / electronic architecture description of, vehicles 基于车辆电气/电子架构描述的汽车领域硬件在环测试系统的快速规范

Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping Pub Date : 2010-06-08 DOI: 10.1109/RSP.2010.5656344

Martin Hillenbrand, M. Heinz, K. Müller-Glaser

{"title":"Rapid specification of hardware-in-the-loop test systems in the automotive domain based on the electric / electronic architecture description of, vehicles","authors":"Martin Hillenbrand, M. Heinz, K. Müller-Glaser","doi":"10.1109/RSP.2010.5656344","DOIUrl":"https://doi.org/10.1109/RSP.2010.5656344","url":null,"abstract":"The fast growth of complexity of modern cars, motorbikes and commercial vehicles continues. Although the number of applied Electronic Control Units (ECUs) decreases [1], they have to fulfill more and more functions concerning performance, comfort and safety [2], [3]. The electric and electronic architecture (EEA) of a vehicle forms the basis for those features and functionalities. An elaborated and evaluated EEA is developed in the concept phases of the vehicle development lifecycle. For a short time, the tool PREEvision offers the possibilities to model EEAs considering different views to the architecture (requirements, software, hardware, wiring harness, topology, etc.). For test and evaluation of the vehicle's functionalities, Hardware in the Loop (HiL) technology is utilized to cover the integration phase of hardware and software. The specification and design of HiL test systems (HiL-TS) is a complex and time-consuming procedure that can be supported by information about electric and electronic artifacts and their relationship, both available in the EEA model. This paper presents an approach for rapid specification, development and application of HiL-TSs as well as rapidly prototyping systems.","PeriodicalId":133782,"journal":{"name":"Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123324873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Scenario path identification for distributed systems: A graph based approach 分布式系统的场景路径识别:基于图的方法

Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping Pub Date : 2010-06-08 DOI: 10.1109/RSP.2010.5656332

A. Kanjilal, S. Sengupta, S. Bhattacharya

{"title":"Scenario path identification for distributed systems: A graph based approach","authors":"A. Kanjilal, S. Sengupta, S. Bhattacharya","doi":"10.1109/RSP.2010.5656332","DOIUrl":"https://doi.org/10.1109/RSP.2010.5656332","url":null,"abstract":"With increased complexity of software systems being developed; analysis of use case scenarios is gaining importance leading to effective test case identification during early part of the life cycle. Existing approaches provide various methods for analysis of UML activity diagrams and scenario path identification based on graph models of activity diagrams. In most cases these methods consider a single activity diagram. However use case scenarios may span multiple activity diagrams, which have become quite common with distributed development of software systems. In this paper we propose Activity Relationship graph model that depicts the interrelationship of activity diagrams modeling a use case. Activity Relationship graph ARG is a hierarchical graph where each node depicts an activity diagram modeled as activity diagram graph (AG). We also define a set of metrics named Use case Scenario Paths (USP) that measures the minimum number of independent paths in ARG. An algorithm is proposed to analyze ARG and derive the number of Use case Scenario Paths. This gives a measure of the number of test paths for a requirement based on analysis models early in the life cycle.","PeriodicalId":133782,"journal":{"name":"Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128821312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Rapid prototyping for digital signal processing systems using Parameterized Synchronous Dataflow graphs 使用参数化同步数据流图的数字信号处理系统的快速原型

Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping Pub Date : 2010-06-08 DOI: 10.1109/RSP.2010.5656423

Hsiang-Huang Wu, Hojin Kee, N. Sane, W. Plishker, S. Bhattacharyya

{"title":"Rapid prototyping for digital signal processing systems using Parameterized Synchronous Dataflow graphs","authors":"Hsiang-Huang Wu, Hojin Kee, N. Sane, W. Plishker, S. Bhattacharyya","doi":"10.1109/RSP.2010.5656423","DOIUrl":"https://doi.org/10.1109/RSP.2010.5656423","url":null,"abstract":"Parameterized Synchronous Dataflow (PSDF) has been used previously for abstract scheduling and as a model for architecting embedded software and FPGA implementations. PSDF has been shown to be attractive for these purposes due to its support for flexible dynamic reconfiguration, and efficient quasi-static scheduling. To apply PSDF techniques more deeply into the design flow, support for comprehensive functional simulation and efficient hardware mapping is important. By building on the DIF (Dataflow Interchange Format), which is a design language and associated software package for developing and experimenting with dataflow-based design techniques for signal processing systems, we have developed a tool for functional simulation of PSDF specifications. This simulation tool allows designers to model applications in PSDF and simulate their functionality, including use of the dynamic parameter reconfiguration capabilities offered by PSDF. Based on this simulation tool, we also present a systematic design methodology for applying PSDF to the design and implementation of digital signal processing systems, with emphasis on FPGA-based systems for signal processing. We demonstrate capabilities for rapid and accurate prototyping offered by our proposed design methodology, along with its novel support for PSDF-based FPGA system implementation.","PeriodicalId":133782,"journal":{"name":"Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133227277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Title page 标题页

Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping Pub Date : 1900-01-01 DOI: 10.5750/ejpch.v4i3.1122.s135

Missouri Lawyers

引用次数: 0

Host-compiled simulation of multi-core platforms 多核平台主机编译仿真

Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping Pub Date : 1900-01-01 DOI: 10.1109/RSP.2010.5656355

A. Gerstlauer

引用次数: 0

RSP 2010 chairs and committees RSP 2010主席和委员会

Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping Pub Date : 1900-01-01 DOI: 10.1109/rsp.2010.5656440

引用次数: 0

RSP 2010 chairs and committees RSP 2010主席和委员会

Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping Pub Date : 1900-01-01 DOI: 10.1109/rsp.2010.5656441

引用次数: 0