An FPGA based semi-parallel architecture for higher order Moving Target Indication (MTI) processing

Zulfiqar Ali, A. Arshad, U. Razzaq
{"title":"An FPGA based semi-parallel architecture for higher order Moving Target Indication (MTI) processing","authors":"Zulfiqar Ali, A. Arshad, U. Razzaq","doi":"10.1109/RSP.2010.5656326","DOIUrl":null,"url":null,"abstract":"The design and implementation of a higher order Moving Target Indication (MTI) engine is presented. This is part of a single chip radar signal processor also incorporating the subsequent algorithms. The bottleneck in use of higher order filters for MTI is not an algorithmic one but one related to implementation. Thus the challenge is to minimize area utilization and achieve the required speed. The proposed architecture employs the use of multiple offchip memory banks for achieving the required memory bandwidth and use of dedicated FPGA resources for area minimization. The requirement of stacking a large number of radar returns in memory and then reading them all for filtering within a single return time demands a parallel memory reading and data processing approach. But this demand has to be balanced with the requirement to consume as little area as possible to leave room for the following algorithms. Considering these constraints, a semi parallel architecture employing multiple filters, each built around a DSP48 slice configured as a Multiply Accumulate (MACC) unit in a time shared manner is used. An analysis of various factors that affect speed and area is also made. The architecture is implemented on a Virtex-4SX35 FPGA using Xilinx XtremeDSP Kit. The design is tested using unprocessed baseband data from a TA-10K air traffic control radar. Results show a marked improvement in the clutter suppression capability of the radar. The design achieves the required speed using only 7% of the available FPGA slices. Thus, not only can the other algorithms be implemented on the same chip but there is room for enhancements as well.","PeriodicalId":133782,"journal":{"name":"Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping","volume":"83 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 2010 21st IEEE International Symposium on Rapid System Protyping","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RSP.2010.5656326","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

Abstract

The design and implementation of a higher order Moving Target Indication (MTI) engine is presented. This is part of a single chip radar signal processor also incorporating the subsequent algorithms. The bottleneck in use of higher order filters for MTI is not an algorithmic one but one related to implementation. Thus the challenge is to minimize area utilization and achieve the required speed. The proposed architecture employs the use of multiple offchip memory banks for achieving the required memory bandwidth and use of dedicated FPGA resources for area minimization. The requirement of stacking a large number of radar returns in memory and then reading them all for filtering within a single return time demands a parallel memory reading and data processing approach. But this demand has to be balanced with the requirement to consume as little area as possible to leave room for the following algorithms. Considering these constraints, a semi parallel architecture employing multiple filters, each built around a DSP48 slice configured as a Multiply Accumulate (MACC) unit in a time shared manner is used. An analysis of various factors that affect speed and area is also made. The architecture is implemented on a Virtex-4SX35 FPGA using Xilinx XtremeDSP Kit. The design is tested using unprocessed baseband data from a TA-10K air traffic control radar. Results show a marked improvement in the clutter suppression capability of the radar. The design achieves the required speed using only 7% of the available FPGA slices. Thus, not only can the other algorithms be implemented on the same chip but there is room for enhancements as well.
基于FPGA的高阶运动目标指示(MTI)处理半并行结构
介绍了一种高阶运动目标指示(MTI)引擎的设计与实现。这是单片雷达信号处理器的一部分,也包含了后续算法。在MTI中使用高阶滤波器的瓶颈不是算法问题,而是与实现有关的问题。因此,挑战在于最小化面积利用率并达到所需的速度。所提出的架构采用使用多个片外存储器组来实现所需的存储器带宽,并使用专用FPGA资源来实现面积最小化。在存储器中堆叠大量雷达回波,然后在单个回波时间内读取它们进行滤波,这一要求要求并行存储器读取和数据处理方法。但是,这种需求必须与消耗尽可能少的面积的要求相平衡,以便为以下算法留出空间。考虑到这些限制,我们使用了一种采用多个滤波器的半并行架构,每个滤波器都围绕一个DSP48片构建,并以时间共享的方式配置为Multiply Accumulate (MACC)单元。分析了影响速度和面积的各种因素。该架构使用Xilinx XtremeDSP Kit在Virtex-4SX35 FPGA上实现。该设计使用来自TA-10K空中交通管制雷达的未处理基带数据进行测试。结果表明,雷达杂波抑制能力明显提高。该设计仅使用7%的可用FPGA片就实现了所需的速度。因此,不仅可以在同一芯片上实现其他算法,而且还有增强的空间。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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