First International Symposium on Networks-on-Chip (NOCS'07)最新文献_第4页

A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs VDSM设计中用于全局互连的低延迟和低功耗混合插入方法

First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.4

Shuming Chen, Xiangyuan Liu

{"title":"A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs","authors":"Shuming Chen, Xiangyuan Liu","doi":"10.1109/NOCS.2007.4","DOIUrl":"https://doi.org/10.1109/NOCS.2007.4","url":null,"abstract":"Current VLSI designs face a serious performance bottleneck due to reverse scaling of global interconnects as CMOS technology scales into VDSM regime. Interconnections techniques which decrease delay, power, and ensure signal integrity, play an important role in the growth of semiconductor industry into future generations. In this paper we present a novel hybrid insertion methodology for on-chip global interconnects. It takes advantage of repeaters and low-swing differential-signaling transceivers on driving long wires in different length, and optimally inserts them along the wires in order to decrease delay, power and gate area cost of interconnects. Simulation results using HSPICE for 0.18mum process showed that delay, power, delay-energy-product (EDP) and gate area cost were considerably decreased compared with other approaches available. Moreover, its computational technique is relatively easy and not limited to a specific low-swing differential-signaling transceiver. Therefore the methodology is very suitable for integration in EDA tool flow and beneficial for the reuse of low-swing differential-signaling transceivers","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127561006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

On the Design of a Photonic Network-on-Chip 一种光子片上网络的设计

First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.35

A. Shacham, K. Bergman, L. Carloni

引用次数: 308

Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC NoC实际芯片实现问题的解决方案及其在以内存为中心的NoC中的应用

First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.40

Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, H. Yoo

{"title":"Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC","authors":"Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, H. Yoo","doi":"10.1109/NOCS.2007.40","DOIUrl":"https://doi.org/10.1109/NOCS.2007.40","url":null,"abstract":"This paper describes real chip implementation issues of network-on-chip (NoC) and their solutions along with series of chip design examples. The solutions described in this paper cover both architectural aspects and circuit level techniques for practical chip implementation of NoC. As for architecture level solutions, topology selection, chip-aware protocol design, and on-chip serialization (OCS) for link area reduction are explained. For circuit level techniques, SERDES and synchronizer design, crossbar switch partial activation, and low-voltage link are presented as the foundations for power and area efficient NoC implementation. Regarding presented solutions for NoC implementation, this paper proposes memory centric NoC (MC-NoC) for homogeneous multi processor SoC (MPSoC). Flexibility and feasibility of task mapping on homogeneous SoC is the key feature of the MC-NoC. 8 dual port SRAMs connected to crossbar switches in hierarchical star topology network facilitate data communication between processors, regardless of task mapping into the MC-NoC. Experimental result obtained by mapping edge detection tasks on the MC-NoC in various configurations shows almost constant performance. This result proves the effectiveness of the proposed architecture. The MC-NoC based SoC is also implemented on TSMC 0.18 um process technology","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133396050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 38

Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases 片上网络多用例配置中的权衡

First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.45

Andreas Hansson, K. Goossens

{"title":"Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases","authors":"Andreas Hansson, K. Goossens","doi":"10.1109/NOCS.2007.45","DOIUrl":"https://doi.org/10.1109/NOCS.2007.45","url":null,"abstract":"Systems on chip (SoC) are becoming increasingly complex, with a large number of applications integrated on the same chip. Such a system often supports a large number of use-cases and is dynamically reconfigured when platform conditions or user requirements change. Networks on chip (NoC) offer the designer unsurpassed runtime flexibility. This flexibility stems from the programmability of the individual routers and network interfaces. When a change in use-case occurs, the application task graph and the network connections change. To mitigate the complexity in programming the many registers controlling the NoC, an abstraction in the form of a configuration library is needed. In addition, such a library must leave the modified system in a consistent state, from which normal operation can continue. In this paper we present the facilities for controlling change in a reconfigurable NoC. We show the architectural additions and the many trade-offs in the design of a run-time library for NoC reconfiguration. We qualitatively and quantitatively evaluate the performance, memory requirements, predictability and reusability of the different implementations","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"606 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134186920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 67

Fast, Accurate and Detailed NoC Simulations 快速，准确和详细的NoC模拟

First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.18

P. T. Wolkotte, P. Hölzenspies, G. Smit

引用次数: 90

On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus 小区宽带引擎元件互连总线性能表征研究

First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.34

Thomas William Ainsworth, T. Pinkston

{"title":"On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus","authors":"Thomas William Ainsworth, T. Pinkston","doi":"10.1109/NOCS.2007.34","DOIUrl":"https://doi.org/10.1109/NOCS.2007.34","url":null,"abstract":"With the rise of multicore computing, the design of on-chip networks (or networks on chip) has become an increasingly important component of computer architecture. The cell broadband engine's element interconnect bus (EIB), with its four data rings and shared command bus for end-to-end control, supports twelve nodes - more than most mainstream on-chip networks, which makes it an interesting case study. As a first step toward understanding the design and performance of on-chip networks implemented within the context of a commercial multicore chip, this paper analytically evaluates the EIB network using conventional latency and throughput characterization methods as well as using a recently proposed 5-tuple latency characterization model for on-chip networks. These are used to identify the end-to-end control component of the EIB (i.e., the shared command bus) as being the main bottleneck to achieving minimal, single-cycle latency and maximal 307.2 GB/sec raw effective bandwidth provided natively by the EIB. This can be exacerbated by poorly designed cell software, which can have significant impact on the utilization of the EIB. The main findings from this study are that the end-to-end control of the EIB influenced by software running on the cell has inherent scaling problems and serves as the main limiter to overall network performance. Thus, end-to-end effects must not be overlooked when designing efficient networks on chip","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116585211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 39

Reflections on 10 Years as a Commercial On-Chip Interconnect Provider 作为商业片上互连供应商10年的思考

First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.38

D. Wingard

引用次数: 0

The Impact of Higher Communication Layers on NoC Supported MP-SoCs 更高通信层对NoC支持的mp - soc的影响

First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.41

T. Marescaux, E. Brockmeyer, H. Corporaal

{"title":"The Impact of Higher Communication Layers on NoC Supported MP-SoCs","authors":"T. Marescaux, E. Brockmeyer, H. Corporaal","doi":"10.1109/NOCS.2007.41","DOIUrl":"https://doi.org/10.1109/NOCS.2007.41","url":null,"abstract":"Multi-processor systems-on-chip use networks-on-chip (NoC) as a communication backbone to tackle the communication between processors and multi-level memory hierarchies. Inter-processor communication has a high impact on the NoC traffic but, to this day, there have been few detailed studies. Based on a realistic case study, we present a contrastive comparison of cache-based versus scratch-pad managed inter-processor communication for (distributed shared-memory) multiprocessor systems-on-chip. The platforms we target use six DSP nodes and a shared L2 memory, interconnected by a packet-switched network-on-chip with differentiated services. The first version of the platform uses caches to perform inter-processor communication whereas the second one uses a novel type of distributed DMA to help performing scratch-pad management. With detailed simulation results we show that the scratchpad application mapping has the best overall performance, that it helps smoothing NoC traffic and that it is not sensitive to the quality-of-service (QoS) used. We furthermore demonstrate that, on the contrary, cache-based MP-SoCs are very sensitive to the QoS level and that they generate significantly more NoC traffic than their scratch-pad counterpart. We recommend, where possible, to use scratch-pad management for NoC supported MP-SoCs as it yields performant, predictable results and can benefit from platform virtualization to achieve composability of applications","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131711733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

Implementation and Evaluation of a Dynamically Routed Processor Operand Network 动态路由处理器操作数网络的实现与评价

First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-01 DOI: 10.1109/NOCS.2007.23

Paul V. Gratz, K. Sankaralingam, H. Hanson, P. Shivakumar, Robert G. McDonald, S. Keckler, D. Burger

{"title":"Implementation and Evaluation of a Dynamically Routed Processor Operand Network","authors":"Paul V. Gratz, K. Sankaralingam, H. Hanson, P. Shivakumar, Robert G. McDonald, S. Keckler, D. Burger","doi":"10.1109/NOCS.2007.23","DOIUrl":"https://doi.org/10.1109/NOCS.2007.23","url":null,"abstract":"Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets, tight coupling between processor microarchitecture and network architecture is one of the keys to improving processor performance. This paper presents the design, implementation and evaluation of the TRIPS operand network (OPN). The TRIPS OPN is a 5times5, dynamically routed, 2D mesh micronet that is integrated into the TRIPS microprocessor core. The TRIPS OPN is used for operand passing, register file I/O, and primary memory system I/O. We discuss in detail the OPN design, including the unique features that arise from its integration with the processor core, such as its connection to the execution unit's wakeup pipeline and its in flight mis-speculated traffic removal. We then evaluate the performance of the network under synthetic and realistic loads. Finally, we assess the processor performance implications of OPN design decisions with respect to the end-to-end latency of OPN packets and the OPN's bandwidth","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131181056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 60