First International Symposium on Networks-on-Chip (NOCS'07)最新文献_第3页

Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures 双同步FIFO同步电路通信非常适合于GALS体系结构的片上网络

First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.14

I. Panades, A. Greiner

引用次数: 122

Transaction-Based Communication-Centric Debug 基于事务的以通信为中心的调试

First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.46

K. Goossens, B. Vermeulen, R. .. Steeden, M. Bennebroek

{"title":"Transaction-Based Communication-Centric Debug","authors":"K. Goossens, B. Vermeulen, R. .. Steeden, M. Bennebroek","doi":"10.1109/NOCS.2007.46","DOIUrl":"https://doi.org/10.1109/NOCS.2007.46","url":null,"abstract":"The behaviour of systems on chip (SOC) is complex because they contain multiple processors that interact through concurrent interconnects, such as networks on chip (NOC). Debugging such SOCs is hard. Based on a classification of debug scope and granularity, we propose that debugging should be communication-centric and based on transactions. Communication-centric debug focuses on the communication and the synchronisation between the IP blocks, which are implemented by the interconnect using transactions. We define and implement a modular debug architecture, based on NOC, monitors, and a dedicated high-speed event-distribution broadcast interconnect. The manufacturing-test scan chains and IEEE1149.1 test access ports (TAP) are re-used for configuration and debug data read-out. Our debug architecture requires only small changes to the functional architecture. The additional area cost is limited to the monitors and the event distribution interconnect, which are 4.5% of the NOC area, or less than 0.2% of the SOC area. The debug architecture runs at NOC functional speed and reacts very quickly to debug events to stop the SOC close in time to the condition that raised the event. The speed at which data is retrieved from the SOC after stopping using the TAP is 10 MHz. We prove our concepts and architecture with a gate-level implementation that includes the NOC, event distribution interconnect, and clock, reset, and TAP controllers. We include gate-level signal traces illustrating debug at message and transaction levels","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115851953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 63

ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC 异步系统建模的系统语言扩展ASC及其在异步NoC中的应用

First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.12

Cedric Koch-Hofer, M. Renaudin, Y. Thonnart, P. Vivet

引用次数: 20

Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips 基于区域的路由:一种解决片上网络中硬件不可靠的有效路由机制

First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.39

J. Flich, A. Mejia, P. López, J. Duato

{"title":"Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips","authors":"J. Flich, A. Mejia, P. López, J. Duato","doi":"10.1109/NOCS.2007.39","DOIUrl":"https://doi.org/10.1109/NOCS.2007.39","url":null,"abstract":"The design of scalable and reliable interconnection networks for system on chips (SoCs) introduce new design constraints not present in current multicomputer systems. Although regular topologies are preferred for building NoCs, heterogeneous blocks, fabrication faults and reliability issues derived from the high integration scale may lead to irregular topologies. In this situation, efficient routing becomes a challenge. Although table-based routing allows the use of most routing algorithms on any topology, it does not scale in terms of latency and area. In this paper we propose the region-based routing mechanism that avoids the scalability problems of table-based solutions. From an initial topology and routing algorithm, the mechanism groups, at every switch, destinations into different regions based on the output ports. By doing this, redundant routing information typically found in routing tables is eliminated. Evaluation results show that the mechanism requires only four regions to support several routing algorithms in a 2D mesh with no performance degradation. Moreover, when dealing with link failures, our results indicate that the mechanism combined with the segment-based routing algorithm is able to pack all the routing information into eight regions providing high throughput. The paper provides also a simple and efficient hardware implementation of the mechanism requiring only 240 logic gates per switch to support eight regions in a 2D mesh topology","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132506930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 82

Implications of Rent's Rule for NoC Design and Its Fault-Tolerance Rent’s规则对NoC设计的启示及其容错性

First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.26

Daniel Greenfield, A. Banerjee, Jeong-Gun Lee, S. Moore

引用次数: 64

A Power and Energy Exploration of Network-on-Chip Architectures 片上网络架构的功率与能源探索

First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.6

A. Banerjee, R. Mullins, S. Moore

引用次数: 101

A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network 一种新的基于低复杂度网格的片上网络二项映射与优化算法

First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.5

Wein-Tsung Shen, Chih-Hao Chao, Yu-Kuang Lien, A. Wu

引用次数: 88

A Study of NoC Exit Strategies 国有石油公司退出策略研究

First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.7

Mikael Millberg, A. Jantsch

引用次数: 1

Approaching Ideal NoC Latency with Pre-Configured Routes 用预配置路由逼近理想NoC延迟

First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.10

George Michelogiannakis, D. Pnevmatikatos, M. Katevenis

{"title":"Approaching Ideal NoC Latency with Pre-Configured Routes","authors":"George Michelogiannakis, D. Pnevmatikatos, M. Katevenis","doi":"10.1109/NOCS.2007.10","DOIUrl":"https://doi.org/10.1109/NOCS.2007.10","url":null,"abstract":"In multi-core ASICs, processors and other compute engines need to communicate with memory blocks and other cores with latency as close as possible to the ideal of a direct buffered wire. However, current state of the art networks-on-chip (NoCs) suffer, at best, latency of one clock cycle per hop. We investigate the design of a NoC that offers close to the ideal latency in some preferred, run-time configurable paths. Processors and other compute engines may perform network reconfiguration to guarantee low latency over different sets of paths as needed. Flits in non-preferred paths are given lower priority than flits in preferred ones, and suffer a delay of one clock cycle per hop when there is no contention. To achieve our goal, we use the \"mad-postman\" technique: every incoming flit is eagerly (i.e. speculatively) forwarded to the input's preferred output, if any. This is accomplished with the mere delay of a single pre-enabled tri-state driver. We later check if that decision was correct, and if not, we forward the flit to the proper output. Incorrectly forwarded flits are classified as dead and eliminated in later hops. We use a 2D mesh topology tailored for processor-memory communication, and a modified version of XY routing that remains deadlock-free. Performance gains are significant and can be proven greatly useful in other application domains as well","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122450674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 52

QNoC Asynchronous Router with Dynamic Virtual Channel Allocation 动态虚拟信道分配的QNoC异步路由器

First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.36

R. Dobkin, R. Ginosar, I. Cidon

引用次数: 33