First International Symposium on Networks-on-Chip (NOCS'07)最新文献

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NoC-Based FPGA: Architecture and Routing 基于noc的FPGA:架构与路由
First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.31
R. Gindin, I. Cidon, I. Keidar
{"title":"NoC-Based FPGA: Architecture and Routing","authors":"R. Gindin, I. Cidon, I. Keidar","doi":"10.1109/NOCS.2007.31","DOIUrl":"https://doi.org/10.1109/NOCS.2007.31","url":null,"abstract":"We present a novel network-on-chip-based architecture for future programmable chips (FPGAs). A key challenge for FPGA design is supporting numerous highly variable design instances with good performance and low cost. Our architecture minimizes the cost of supporting a wide range of design instances with given throughput requirements by balancing the amount of efficient hard-coded NoC infrastructure and the allocation of \"soft\" networking resources at configuration time. Although traffic patterns are design-specific, the physical link infrastructure is a performance bottleneck, and hence should be hard-coded. It is therefore important to employ routing schemes that allow for high flexibility to efficiently accommodate different traffic patterns during configuration. We examine the required capacity allocation for supporting a collection of typical traffic patterns on such chips under a number of routing schemes. We propose a new routing scheme, weighted ordered toggle (WOT), and show that it allows high design flexibility with low infrastructure cost. Moreover, WOT utilizes simple, small-area, on-chip routers, and has low memory demands","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125116998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 76
Access Regulation to Hot-Modules in Wormhole NoCs 虫洞noc热模块的接入规则
First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.8
Isask'har Walter, I. Cidon, R. Ginosar, A. Kolodny
{"title":"Access Regulation to Hot-Modules in Wormhole NoCs","authors":"Isask'har Walter, I. Cidon, R. Ginosar, A. Kolodny","doi":"10.1109/NOCS.2007.8","DOIUrl":"https://doi.org/10.1109/NOCS.2007.8","url":null,"abstract":"Network on chip (NoC) may be the primary interconnect mechanism for future systems-on-chip (SoC). Real-life SoCs typically include hot-modules such as DRAM controller or floating point unit, which are bandwidth limited and in high demand by other units. In this paper we demonstrate that the mere existence of one or more hot-modules in a wormhole-based NoC dramatically reduces network efficiency and causes an unfair allocation of system resources. We demonstrate that a single hot-module destroys the performance of the entire SoC, even if network resources are over-provisioned. In order to resolve the hot-module effect, we introduce a novel low-cost credit based distributed access regulation technique that fairly allocates access rights to the hot-module. Unlike other methods, this technique directly addresses the root cause of network buffer congestion phenomena. Using simulation, we show the effectiveness of the suggested mechanism in various NoC scenarios","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128247319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
The Power of Priority: NoC Based Distributed Cache Coherency 优先级的力量:基于NoC的分布式缓存一致性
First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.42
Evgeny Bolotin, Zvika Guz, I. Cidon, R. Ginosar, A. Kolodny
{"title":"The Power of Priority: NoC Based Distributed Cache Coherency","authors":"Evgeny Bolotin, Zvika Guz, I. Cidon, R. Ginosar, A. Kolodny","doi":"10.1109/NOCS.2007.42","DOIUrl":"https://doi.org/10.1109/NOCS.2007.42","url":null,"abstract":"The paper introduces network-on-chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance chip multi processors (CMPs). We address previously proposed CMP architectures based on non uniform cache architecture (NUCA) over NoC, analyze basic memory transactions and translate them into a set of network transactions. We first show how a simple, generic NoC which is equipped with needed module interface functionalities can provide infrastructure for the coherent access of both static and dynamic NUCA. Then we show how several low cost mechanisms incorporated into such a vanilla NoC can facilitate CMP and boost performance of a cache coherent NUCA CMP. The basic mechanism is based on priority support embedded in the NoC, which differentiates between short control signals and long data messages to achieve a major reduction in cache access delay. The low cost priority-based NoC is extremely useful for increasing performance of almost any other CMP transaction. Priority-based NoC along with the discussed NoC interfaces are evaluated in detail using CMP-NoC simulations across several SPLASH-2 benchmarks and static Web content serving benchmarks showing substantial L2 cache access delay reduction and overall program speedup","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130078948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 79
Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip 面向测试的异步片上网络架构的实现
First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.24
Xuan-Tu Tran, J. Durupt, Y. Thonnart, F. Bertrand, V. Beroulle, C. Robach
{"title":"Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip","authors":"Xuan-Tu Tran, J. Durupt, Y. Thonnart, F. Bertrand, V. Beroulle, C. Robach","doi":"10.1109/NOCS.2007.24","DOIUrl":"https://doi.org/10.1109/NOCS.2007.24","url":null,"abstract":"In order to improve the testability of asynchronous NoCs, we have developed a design-for-test (DfT) architecture. In this architecture, each asynchronous network node is surrounded by an asynchronous test wrapper and the network communication channels are reused to establish high throughput TAMs. A special block, the generator-analyzer-controller (GAC) unit, has also been developed to generate test vectors, to control test flows, and to analyze the test results. This unit can be implemented on-chip or off-chip (in our experiments, it has been implemented off-chip). The operation of the test wrappers is controlled by a dedicated 2-bit configuration channel. Thanks to its scalability and versatility, the proposed architecture can be configured to adapt to any NoC topology and to any specific application.","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128085035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Architecture of the Scalable Communications Core 可扩展通信核心的体系结构
First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.11
J. D. Hoffman, David Arditti Ilitzky, A. Chun, A. Chapyzhenka
{"title":"Architecture of the Scalable Communications Core","authors":"J. D. Hoffman, David Arditti Ilitzky, A. Chun, A. Chapyzhenka","doi":"10.1109/NOCS.2007.11","DOIUrl":"https://doi.org/10.1109/NOCS.2007.11","url":null,"abstract":"The scalable communications core (SCC) is a power- and area-efficient solution for physical layer (PHY) and lower MAC processing of concurrent multiple wireless protocols. Our architecture consists of coarse-grained, heterogeneous, programmable accelerators connected via a packet-based 3-ary 2-cube network on chip (NoC). The combination of the accelerators, which were developed for key communications operations, and the NoC results in an architecture that is flexible for multiple protocols, extensible for future standards and scalable to support multiple simultaneous streams","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115057291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Design Technologies for Networks on Chips 芯片上网络的设计技术
First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.16
G. Micheli
{"title":"Design Technologies for Networks on Chips","authors":"G. Micheli","doi":"10.1109/NOCS.2007.16","DOIUrl":"https://doi.org/10.1109/NOCS.2007.16","url":null,"abstract":"Summary form only given. Networks on chips provide structured solutions for fast and low-power interconnect, but need to be adapted to the performance and physical design requirements of the host chip. Efficient and optimal design of such networks is an error-prone, tedious and time-consuming task. Thus, NoCs require design environments in which the network can be instantiated and tuned automatically, and where the designer steers the design by providing high level models of requirements and constraints. This talk would survey the state of the art in design automation for NoCs","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123130285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study 正式验证NoC通信架构的通用模型:一个案例研究
First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.1
D. Borrione, A. Helmy, L. Pierre, J. Schmaltz
{"title":"A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study","authors":"D. Borrione, A. Helmy, L. Pierre, J. Schmaltz","doi":"10.1109/NOCS.2007.1","DOIUrl":"https://doi.org/10.1109/NOCS.2007.1","url":null,"abstract":"Networks on chip are emerging as a promising solution for the design of complex systems on a chip, to interconnect manufactured IP cores, and the need to formally guarantee their correctness is crucial. In a NoC centered design, the individual IP's are considered already validated. This paper addresses the validation of the communication infrastructure. A generic formal model for NoC's has been developed and implemented in the ACL2 theorem prover. As an application, the HERMES network has been formalized in this model, and we show that both formal proofs and simulation experiments can be performed in ACL2","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131207075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
NoC Design and Implementation in 65nm Technology 65纳米NoC设计与实现
First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.30
A. Pullini, F. Angiolini, P. Meloni, David Atienza Alonso, S. Murali, L. Raffo, G. Micheli, L. Benini
{"title":"NoC Design and Implementation in 65nm Technology","authors":"A. Pullini, F. Angiolini, P. Meloni, David Atienza Alonso, S. Murali, L. Raffo, G. Micheli, L. Benini","doi":"10.1109/NOCS.2007.30","DOIUrl":"https://doi.org/10.1109/NOCS.2007.30","url":null,"abstract":"As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent. Networks-on-chip (NoCs) have been proposed as a scalable solution to both physical design issues and increasing bandwidth demands. However, this claim has not been fully validated yet, since the design properties and tradeoffs of NoCs have not been studied in detail below the 100 nm threshold. This work is aimed at shedding light on the opportunities and challenges, both expected and unexpected, of NoC design in nanometer CMOS. We present fully working 65 nm NoC designs, a complete NoC synthesis flow and detailed scalability analysis","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115971212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 63
Enabling Technology for On-Chip Interconnection Networks 片上互连网络的使能技术
First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.17
W. Dally
{"title":"Enabling Technology for On-Chip Interconnection Networks","authors":"W. Dally","doi":"10.1109/NOCS.2007.17","DOIUrl":"https://doi.org/10.1109/NOCS.2007.17","url":null,"abstract":"As we enter the era of many-core processors and complex SoCs, on-chip interconnection networks play a dominant role in determining the performance, power, and cost of a system. These networks are critically dependent on a number of underlying technologies: channel, buffer, and switch circuits, router microarchitecture, flow-control and routing methods, and network topology. Too often on-chip networks are built in a naive manner using a ring or mesh topology and standard cell methodology. Compared to this approach, optimized circuits can reduce power by an order of magnitude and an optimized topology can give an additional factor of two to three in area and power efficiency. This talk can explore key enabling technologies for on-chip networks giving a number of examples and identifying opportunities for future research","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"755 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116114613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
An Analytical Approach for Dimensioning Mixed Traffic Networks 混合交通网络维数的一种分析方法
First International Symposium on Networks-on-Chip (NOCS'07) Pub Date : 2007-05-07 DOI: 10.1109/NOCS.2007.9
Per Badlund, A. Jantsch
{"title":"An Analytical Approach for Dimensioning Mixed Traffic Networks","authors":"Per Badlund, A. Jantsch","doi":"10.1109/NOCS.2007.9","DOIUrl":"https://doi.org/10.1109/NOCS.2007.9","url":null,"abstract":"We present an analytical method for analyzing and dimensioning a network based communication architecture. The method is based on the classic (sigma, p) network calculus. We use a TDMA approach for creating logically separated networks which makes statistical methods possible for calculations on best effort traffic, and supports implementation of guaranteed bandwidth services by using virtual circuits with looped containers","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129190102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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