面向测试的异步片上网络架构的实现

Xuan-Tu Tran, J. Durupt, Y. Thonnart, F. Bertrand, V. Beroulle, C. Robach
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引用次数: 8

摘要

为了提高异步noc的可测试性,我们开发了一种面向测试的设计(DfT)架构。在这种体系结构中,每个异步网络节点都被异步测试包装器包围,并且网络通信通道被重用以建立高吞吐量的tam。还开发了一个特殊的块,即生成-分析-控制器(GAC)单元,用于生成测试向量、控制测试流程和分析测试结果。该单元可以在片内或片外实现(在我们的实验中,它已经实现了片外)。测试包装器的操作由专用的2位配置通道控制。由于其可扩展性和多功能性,所提出的体系结构可以配置为适应任何NoC拓扑和任何特定的应用程序。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip
In order to improve the testability of asynchronous NoCs, we have developed a design-for-test (DfT) architecture. In this architecture, each asynchronous network node is surrounded by an asynchronous test wrapper and the network communication channels are reused to establish high throughput TAMs. A special block, the generator-analyzer-controller (GAC) unit, has also been developed to generate test vectors, to control test flows, and to analyze the test results. This unit can be implemented on-chip or off-chip (in our experiments, it has been implemented off-chip). The operation of the test wrappers is controlled by a dedicated 2-bit configuration channel. Thanks to its scalability and versatility, the proposed architecture can be configured to adapt to any NoC topology and to any specific application.
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