The Impact of Higher Communication Layers on NoC Supported MP-SoCs

Abstract

Multi-processor systems-on-chip use networks-on-chip (NoC) as a communication backbone to tackle the communication between processors and multi-level memory hierarchies. Inter-processor communication has a high impact on the NoC traffic but, to this day, there have been few detailed studies. Based on a realistic case study, we present a contrastive comparison of cache-based versus scratch-pad managed inter-processor communication for (distributed shared-memory) multiprocessor systems-on-chip. The platforms we target use six DSP nodes and a shared L2 memory, interconnected by a packet-switched network-on-chip with differentiated services. The first version of the platform uses caches to perform inter-processor communication whereas the second one uses a novel type of distributed DMA to help performing scratch-pad management. With detailed simulation results we show that the scratchpad application mapping has the best overall performance, that it helps smoothing NoC traffic and that it is not sensitive to the quality-of-service (QoS) used. We furthermore demonstrate that, on the contrary, cache-based MP-SoCs are very sensitive to the QoS level and that they generate significantly more NoC traffic than their scratch-pad counterpart. We recommend, where possible, to use scratch-pad management for NoC supported MP-SoCs as it yields performant, predictable results and can benefit from platform virtualization to achieve composability of applications