IEEE Transactions on Emerging Topics in Computing最新文献

{"title":"MFDS-STGCN: Predicting the Behaviors of College Students With Fine-Grained Spatial-Temporal Activities Data","authors":"Dongbo Zhou;Hongwei Yu;Jie Yu;Shuai Zhao;Wenhui Xu;Qianqian Li;Fengyin Cai","doi":"10.1109/TETC.2023.3344131","DOIUrl":"10.1109/TETC.2023.3344131","url":null,"abstract":"Mining and predicting college students behaviors from fine-grained spatial-temporal campus activity data play key roles in the academic success and personal development of college students. Most of the existing behavior prediction methods use shallow learning algorithms such as statistics, clustering, and correlation analysis approaches, which fail to mine the long-term spatial-temporal dependencies and semantic correlations from these fine-grained campus data. We propose a novel multi-fragment dynamic semantic spatial-temporal graph convolution network, named the MFDS-STGCN, on the basis of a spatial-temporal graph convolutional network (STGCN) for the automatic prediction of college students’ behaviors and abnormal behaviors. We construct a dataset including 7.6 million behavioral records derived from approximately 400 students over 140 days to evaluate the effectiveness of the prediction model. Extensive experimental results demonstrate that the proposed method outperforms multiple baseline prediction methods in terms of student behavior prediction and abnormal behavior prediction, with accuracies of 92.60% and 90.84%, respectively. To further enable behavior prediction, we establish an early warning management mechanism. Based on the predictions and analyses of Big Data, education administrators can detect undesirable abnormal behaviors in time and thus implement effective interventions to better guide students' campus lives, ultimately helping them to more effectively develop and grow.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"12 1","pages":"254-265"},"PeriodicalIF":5.9,"publicationDate":"2024-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139947919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A FeFET-Based ADC Offset Robust Compute-In-Memory Architecture for Streaming Keyword Spotting (KWS)","authors":"Yandong Luo;Johan Vanderhaegen;Oleg Rybakov;Martin Kraemer;Niel Warren;Shimeng Yu","doi":"10.1109/TETC.2023.3345346","DOIUrl":"https://doi.org/10.1109/TETC.2023.3345346","url":null,"abstract":"Keyword spotting (KWS) on edge devices requires low power consumption and real-time response. In this work, a ferroelectric field-effect transistor (FeFET)-based compute-in-memory (CIM) architecture is proposed for streaming KWS processing. Compared with the conventional sequential processing scheme, the inference latency is reduced by 7.7 × ∼17.6× without energy efficiency loss. To make the KWS models robust to hardware non-idealities such as analog-to-digital converter (ADC) offset, an offset-aware training scheme is proposed. It consists of ADC offset noise injection and frame-wise normalization. This scheme effectively improves the mean accuracy and chip yield by 1.5%∼5.2%, and 5%∼39%, for TC-ResNet and DS-TC-ResNet (with MatchboxNet configuration), respectively. The proposed CIM architecture is implemented with ferroelectric field-effect transistor technology, with simulated low energy consumption of 1.65 μJ/decision for 12-word keyword spotting using TC-ResNet8.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"12 1","pages":"23-34"},"PeriodicalIF":5.9,"publicationDate":"2023-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140161166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Near-Memory Computing With Compressed Embedding Table for Personalized Recommendation","authors":"Jeongmin Lim;Young Geun Kim;Sung Woo Chung;Farinaz Koushanfar;Joonho Kong","doi":"10.1109/TETC.2023.3345870","DOIUrl":"https://doi.org/10.1109/TETC.2023.3345870","url":null,"abstract":"Deep learning (DL)-based recommendation models play an important role in many real-world applications. However, an embedding layer, which is a key part of the DL-based recommendation models, requires sparse memory accesses to a very large memory space followed by the pooling operations (i.e., reduction operations). It makes the system overprovision memory capacity for model deployment. Moreover, with conventional CPU-based architecture, it is difficult to exploit the locality, causing a huge burden for data transfer between the CPU and memory. To resolve this problem, we propose an embedding vector element quantization and compression method to reduce the memory footprint (capacity) required by the embedding tables. In addition, to reduce the amount of data transfer and memory access, we propose near-memory acceleration hardware with an SRAM buffer that stores the frequently accessed embedding vectors. Our quantization and compression method results in compression ratios of 3.95–4.14 for embedding tables in widely used datasets while negligibly affecting the inference accuracy. Our acceleration technique with 3D stacked DRAM memories, which facilitates the near-memory processing in the logic die with high DRAM bandwidth, leads to 4.9 × –5.4 × embedding layer speedup as compared to the 8-core CPU-based execution while reducing the memory energy consumption by 5.9 × −12.1 ×, on average.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"12 3","pages":"938-951"},"PeriodicalIF":5.1,"publicationDate":"2023-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142143780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integrated Edge Computing and Blockchain: A General Medical Data Sharing Framework","authors":"Zongjin Li;Jie Zhang;Jian Zhang;Ya Zheng;Xunjie Zong","doi":"10.1109/TETC.2023.3344655","DOIUrl":"https://doi.org/10.1109/TETC.2023.3344655","url":null,"abstract":"Medical data sharing is crucial to enhance diagnostic efficiency and improve the quality of medical data analysis. However, related endeavors face obstacles due to insufficient collaboration among medical institutions, and traditional cloud-based sharing platforms lead to concerns regarding security and privacy. To overcome these challenges, the paper introduces MSNET, a novel framework that seamlessly combines blockchain and edge computing. Data traceability and access control are ensured by employing blockchain as a security layer. The blockchain stores only data summaries instead of complete medical data, thus enhancing scalability and transaction efficiency. The raw medical data are securely processed on edge servers within each institution, with data standardization and keyword extraction. To facilitate data access and sharing among institutions, smart contracts are designed to promote transparency and data accuracy. Moreover, a supervision mechanism is established to maintain a trusted environment, provide reliable evidence against dubious data-sharing practices, and encourage institutions to share data voluntarily. This novel framework effectively overcomes the limitations of traditional blockchain solutions, offering an efficient and secure method for medical data sharing and thereby fostering collaboration and innovation in the healthcare industry.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"12 3","pages":"924-937"},"PeriodicalIF":5.1,"publicationDate":"2023-12-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142143714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Joint Partial Offloading and Resource Allocation for Parked Vehicle-Assisted Multi-Access Edge Computing","authors":"Xuan-Qui Pham;Thien Huynh-The;Dong-Seong Kim","doi":"10.1109/TETC.2023.3344133","DOIUrl":"https://doi.org/10.1109/TETC.2023.3344133","url":null,"abstract":"In recent years, parked vehicle-assisted multi-access edge computing (PVMEC) has emerged to expand the computational power of MEC networks by utilizing the opportunistic resources of parked vehicles (PVs) for computation offloading. In this article, we study a joint optimization problem of partial offloading and resource allocation in a PVMEC paradigm that enables each mobile device (MD) to offload its task partially to either the MEC server or nearby PVs. The problem is first formulated as a mixed-integer nonlinear programming problem with the aim of maximizing the total offloading utility of all MDs in terms of the benefit of reducing latency through offloading and the overall cost of using computing and networking resources. We then propose a partial offloading scheme, which employs a differentiation method to derive the optimal offloading ratio and resource allocation while optimizing the task assignment using a metaheuristic solution based on the whale optimization algorithm. Finally, evaluation results justify the superior system utility of our proposal compared with existing baselines.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"12 3","pages":"918-923"},"PeriodicalIF":5.1,"publicationDate":"2023-12-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142143724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Emerging Topics in Computing Information for Authors","authors":"","doi":"10.1109/TETC.2023.3338322","DOIUrl":"https://doi.org/10.1109/TETC.2023.3338322","url":null,"abstract":"","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"11 4","pages":"C2-C2"},"PeriodicalIF":5.9,"publicationDate":"2023-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10349224","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138558047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Toward Designing High-Speed Cost-Efficient Quantum Reversible Carry Select Adders","authors":"Shekoofeh Moghimi;Mohammad Reza Reshadinezhad;Antonio Rubio","doi":"10.1109/TETC.2023.3332426","DOIUrl":"https://doi.org/10.1109/TETC.2023.3332426","url":null,"abstract":"Compared to classical computing implementations, reversible arithmetic adders offer a valuable platform for implementing quantum computation models in digital systems and specific applications, such as cryptography and natural language processing. Reversible logic efficiently prevents energy wastage through thermal dissipation. This study presents a comprehensive exploration introducing new carry-select adders (CSLA) based on quantum and reversible logic. Five reversible CSLA designs are proposed and compared, evaluating various criteria, including speed, quantum cost, and area, compared to previously published schemes. These comparative metrics are formulated for arbitrary n-bit size blocks. Each design type is described generically, capable of implementing carry-select adders of any size. As the best outcome, this study proposes an optimized reversible adder circuit that addresses quantum propagation delay, achieving an acceptable trade-off with quantum cost compared to its counterparts. This article reduces calculation delay by 66%, 73%, 82%, and 87% for 16, 32, 64, and 128 bits, respectively, while maintaining a lower quantum cost in all cases.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"12 3","pages":"905-917"},"PeriodicalIF":5.1,"publicationDate":"2023-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142143743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Extremely Energy-Efficient Non-Linear Function Approximation Framework Using Stochastic Superconductor Devices","authors":"Olivia Chen;Renyuan Zhang;Wenhui Luo;Yanzhi Wang;Nobuyuki Yoshikawa","doi":"10.1109/TETC.2023.3330979","DOIUrl":"10.1109/TETC.2023.3330979","url":null,"abstract":"Recently developed adiabatic quantum-flux-parametron (AQFP) superconducting technology achieves the highest energy efficiency among various superconducting logic families, potentially 10\u0000⁴\u0000-10\u0000⁵\u0000 gain compared with state-of-the-art CMOS. Besides ultra-high energy efficiency, AQFP exhibits two unique characteristics: the deep pipelining nature as all logic gates are clocked and the potential of building stochastic number generators (SNGs) using a single AQFP gate, far more efficient than SNGs implemented in conventional CMOS. These unique characteristics indicate that the AQFP technology is highly compatible with stochastic computing (SC) implementations, where operands are represented by a time-independent bit sequence utilizing the deep pipelining structure of AQFP. To shed some light on the SC-based design methodology on novel superconducting technologies, we propose an AQFP-based non-linear function approximation framework with the fashion of Bernstein polynomials, achieving a general hardware architecture to perform multiple non-linear functions without any extra hardware overhead. Experimental results of 9 common non-linear functions widely used in pattern recognition, signal processing, and neural networks reveal that our work provides outstanding energy efficiency with sufficient computing accuracy. The energy-delay-error-product (EDE\u0000_MAE\u0000P) of the proposed design, in terms of the polynomial degree of 3, 5 and 7, are 3.47 × 10\u0000⁻²⁵\u0000J\u0000<inline-formula><tex-math>$cdot$</tex-math></inline-formula>\u0000s, 3.63 × 10\u0000⁻²⁵\u0000J\u0000<inline-formula><tex-math>$cdot$</tex-math></inline-formula>\u0000s and 6.79 × 10\u0000⁻²⁵\u0000J\u0000<inline-formula><tex-math>$cdot$</tex-math></inline-formula>\u0000s on average, respectively, achieving 5-6 orders better performance than its CMOS counterpart. Further discussions on the measurement results of trial-fabricated AQFP comparators reveal the future research directions of AQFP-based SC implementations.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"12 4","pages":"956-967"},"PeriodicalIF":5.1,"publicationDate":"2023-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135660711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TCAM-GNN: A TCAM-Based Data Processing Strategy for GNN Over Sparse Graphs","authors":"Yu-Pang Wang;Wei-Chen Wang;Yuan-Hao Chang;Chieh-Lin Tsai;Tei-Wei Kuo;Chun-Feng Wu;Chien-Chung Ho;Han-Wen Hu","doi":"10.1109/TETC.2023.3328008","DOIUrl":"10.1109/TETC.2023.3328008","url":null,"abstract":"The graph neural network (GNN) has recently become an emerging research topic for processing non-euclidean data structures since the data used in various popular application domains are usually modeled as a graph, such as social networks, recommendation systems, and computer vision. Previous GNN accelerators commonly utilize the hybrid architecture to resolve the issue of “hybrid computing pattern” in GNN training. Nevertheless, the hybrid architecture suffers from poor utilization of hardware resources mainly due to the dynamic workloads between different phases in GNN. To address these issues, existing GNN accelerators adopt a unified structure with numerous processing elements and high bandwidth memory. However, the large amount of data movement between the processor and memory could heavily downgrade the performance of such accelerators in real-world graphs. As a result, the processing-in-memory architecture, such as the ReRAM-based crossbar, becomes a promising solution to reduce the memory overhead of GNN training. In this work, we present the TCAM-GNN, a novel TCAM-based data processing strategy, to enable high-throughput and energy-efficient GNN training over ReRAM-based crossbar architecture. Several hardware co-designed data structures and placement methods are proposed to fully exploit the parallelism in GNN during training. In addition, we propose a dynamic fixed-point formatting approach to resolve the precision issue. An adaptive data reusing policy is also proposed to enhance the data locality of graph features by the bootstrapping batch sampling approach. Overall, TCAM-GNN could enhance computing performance by 4.25× and energy efficiency by 9.11× on average compared to the neural network accelerators.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"12 3","pages":"891-904"},"PeriodicalIF":5.1,"publicationDate":"2023-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134890608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability Evaluation and Fault Tolerant Design for KLL Sketches","authors":"Zhen Gao;Jinhua Zhu;Pedro Reviriego","doi":"10.1109/TETC.2023.3324331","DOIUrl":"10.1109/TETC.2023.3324331","url":null,"abstract":"Quantile estimation is a fundamental task in Big Data analysis. In order to achieve high-speed estimation with low memory consumption, especially for streaming Big Data processing, data sketches which provide approximate estimates at low overhead are commonly used, and the Karnin-Lang-Liberty (KLL) sketch is one of the most popular options. However, soft errors in KLL memory may significantly degrade estimation performance. In this article, the influence of soft errors on the KLL sketch is considered for the first time. First, the reliability of KLL to soft errors is studied through theoretical analysis and fault injection experiments. The evaluation results show that the errors in the KLL construction phase may cause a large deviation in the estimated value. Then, two protection schemes are proposed based on a single parity check (SPC) and on the incremental property (IP) of the KLL memory. Further evaluation shows that the proposed schemes can significantly improve the reliability of KLL, and even remove the effect SEUs on the highest bits. In particular, the SPC scheme that requires additional memory, provides better protection for middle bit positions than the IP scheme which does not introduce any memory overhead.","PeriodicalId":13156,"journal":{"name":"IEEE Transactions on Emerging Topics in Computing","volume":"12 4","pages":"1002-1013"},"PeriodicalIF":5.1,"publicationDate":"2023-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135214276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}