IEEE Journal of Solid-state Circuits最新文献_第5页

A Digital-Sampling PLL With a Second-Order Noise Shaping SAR ADC Phase Detector

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-03-22 DOI: 10.1109/jssc.2025.3549690

Matthew R. Belz, Zhengqi Xu, Hsiang-Wen Chen, Seungheun Song, Michael P. Flynn

引用次数: 0

Design Considerations of High-Frequency-Reference Fractional-TEXPRESERVE0 PLL: Architecture and Nonidealities 高频参考分数-TEXPRESERVE0 PLL 的设计考虑因素：架构和非理想性

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-03-21 DOI: 10.1109/jssc.2025.3548028

Dihang Yang, David Murphy, Hooman Darabi, Arya Behzad, Richard Ruby, Reed Parker

引用次数: 0

A 9-GHz Low-In-Band Noise Sub-Sampling-Chopper PLL With Charge-Share Canceling Technique

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-03-18 DOI: 10.1109/JSSC.2025.3532504

Xiangjian Kong;Kai Xu;Huanlin Xie;Mingchao Jian;Hao Lian;Robert Bogdan Staszewski;Chunbing Guo

{"title":"A 9-GHz Low-In-Band Noise Sub-Sampling-Chopper PLL With Charge-Share Canceling Technique","authors":"Xiangjian Kong;Kai Xu;Huanlin Xie;Mingchao Jian;Hao Lian;Robert Bogdan Staszewski;Chunbing Guo","doi":"10.1109/JSSC.2025.3532504","DOIUrl":"10.1109/JSSC.2025.3532504","url":null,"abstract":"This article presents a low-jitter sub-sampling chopper phase-locked loop (SS-CPLL) that incorporates a novel chopping charge pump (C-CP) to mitigate 1/f noise in short-channel devices operating at a low supply voltage of 0.75 V. A charge-share cancellation technique is introduced to suppress ripple generated by residual charge from the previous reference period. The chopping modulation further reduces the charge pump’s white noise by filtering out high-order harmonics of folded noise, thereby significantly lowering in-band noise. In addition, a high-swing class-C/F2 voltage-controlled oscillator (VCO) is proposed to optimize out-of-band noise while maintaining low power consumption. Fabricated in 65-nm complementary metal oxide semiconductor (CMOS) with a core area of 0.64 mm2, the SS-CPLL achieves an in-band phase noise of −111.9 dBc/Hz at 1-kHz offset, an integrated jitter of 49.9 fs, and a figure-of-merit (FoM) of −257.1 dB at 9 GHz, while consuming 7.8 mW of power. The proposed SS-CPLL reduces in-band noise by approximately 15 dB compared with a conventional sub-sampling phase-locked loop (SSPLL), while maintaining a similar reference spur level of −58 dBc/Hz. This highlights the effectiveness of the C-CP and charge-share cancellation techniques.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 4","pages":"1384-1396"},"PeriodicalIF":4.6,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143661438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A TTD-Based Fast Precise Localization Enabled by Passive–Active Signal Combiner With Negative-Capacitance Stabilized RAMP

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-03-18 DOI: 10.1109/jssc.2025.3546958

Qiuyan Xu, Aditya Wadaskar, Foad Beheshti, Chung-Ching Lin, Huan Hu, Danijela Cabric, Subhanshu Gupta

引用次数: 0

VISTA: A Memory-Efficient CNN Processor for Video and Image Spatial/Temporal Interpolation Acceleration

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-03-12 DOI: 10.1109/jssc.2025.3547982

Kai-Ping Lin, Jia-Han Liu, Hong-Chuan Liao, Jyun-Yi Wu, Tong Wu, Chao-Tsung Huang

引用次数: 0

A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-03-12 DOI: 10.1109/JSSC.2025.3535888

Sayan Kumar;Teerachot Siriburanon;Sumit Dash;Patchara Sawakewang;Shuja Andrabi;Jon Strange;Khurram Muhammad;Chih-Ming Hung;Robert Bogdan Staszewski

{"title":"A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations","authors":"Sayan Kumar;Teerachot Siriburanon;Sumit Dash;Patchara Sawakewang;Shuja Andrabi;Jon Strange;Khurram Muhammad;Chih-Ming Hung;Robert Bogdan Staszewski","doi":"10.1109/JSSC.2025.3535888","DOIUrl":"10.1109/JSSC.2025.3535888","url":null,"abstract":"We propose a new ping-pong (PP) charge-sharing locking (CSL) phase-locked loop (PLL) architecture that enhances the strength of charge-injection into the oscillator’s LC-tank using complementary charge-sharing capacitors during both positive and negative halves of the reference clock, effectively achieving an implicit <inline-formula> <tex-math>$2times $ </tex-math></inline-formula> reference frequency multiplication. The design includes a simultaneous frequency-tracking loop (FTL) and duty-cycle calibration (DCC) loop for robust PVT tracking, employing an ultralow-power bang-bang phase-detector (BB-PD). A class-F3 oscillator along with its third harmonic extractor generate the ~27 GHz output. Implemented in 28 nm CMOS, the PP-CSL PLL demonstrates a threefold increase in injection strength compared to the conventional CSL PLLs, while resolving the load-modulation issue and improving the reference spur by ~15 dB. It achieves an ultralow rms jitter of 42 fs with a power consumption of only 14 mW, resulting in an outstanding jitter-normalized figure of merit (<inline-formula> <tex-math>$rm FoM_{{mathrm { jitter}}{-}N}$ </tex-math></inline-formula>) of −276.6 dB.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 4","pages":"1368-1383"},"PeriodicalIF":4.6,"publicationDate":"2025-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10924718","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143607803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-03-11 DOI: 10.1109/JSSC.2025.3545483

Junhui Gu;John Ma;Azhar Ahmed Chowdhury;Jianmin Guo;Xin Zhang;Jackson Ding;Hui Wang;Ken Chang

{"title":"A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring","authors":"Junhui Gu;John Ma;Azhar Ahmed Chowdhury;Jianmin Guo;Xin Zhang;Jackson Ding;Hui Wang;Ken Chang","doi":"10.1109/JSSC.2025.3545483","DOIUrl":"10.1109/JSSC.2025.3545483","url":null,"abstract":"This article presents a high-density, single-ended non return to zero (NRZ) chiplet I/O implemented with 3 nm CMOS technology on a 2.5-D chip-on-wafer-on-substrate (CoWoS) interposer, accommodating trace lengths up to 2 mm. The design features 216 data lanes, each operating at 32 Gb/s. For the tested 2-mm trace, the channel insertion loss and crosstalk at the Nyquist frequency are −2.4 and −18.1 dB, respectively. The receiver (RX) includes real-time clock data recovery (CDR) and a bathtub monitor for each lane, optimizing sampling point adjustments and tracking phase drift across voltage and temperature variations. With all lanes active, the physical layer (PHY) achieves a density of 3.84 Tb/s/mm and operates with a power consumption of 0.36 pJ/bit. The worst-performing lane shows a 0.342 UI opening at a bit error rate (BER) of 1e<sup>−12</sup>, and an interpolated 0.331 UI opening at a BER of 1e<sup>−15</sup> when running at 32 Gb/s. Additionally, results for 25 Gb/s operation are included as a lower power alternative. This article will discuss the design details and trade-offs of the transceiver.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 4","pages":"1289-1298"},"PeriodicalIF":4.6,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143598888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

MINOTAUR: A Posit-Based 0.42–0.50-TOPS/W Edge Transformer Inference and Training Accelerator

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-03-06 DOI: 10.1109/JSSC.2025.3545731

Kartik Prabhu;Robert M. Radway;Jeffrey Yu;Kai Bartolone;Massimo Giordano;Fabian Peddinghaus;Yonatan Urman;Win-San Khwa;Yu-Der Chih;Meng-Fan Chang;Subhasish Mitra;Priyanka Raina

引用次数: 0

A Simultaneous Dual-Carrier Transformer-Coupled Passive Mixer-First Receiver Front-End Supporting Blocker Suppression

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-03-06 DOI: 10.1109/jssc.2025.3546082

Jamie C. Ye, Alain H. Antón, Sanaz Sadeghi, Russ H. Huang, Alyosha C. Molnar

引用次数: 0

A 28-nm 142-mW Motion-Control SoC for Autonomous Mobile Robots

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2025-03-04 DOI: 10.1109/jssc.2025.3543621

I-Ting Lin, Zih-Sing Fu, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang

引用次数: 0