IEEE Journal of Solid-state Circuits最新文献_第6页

A 150-GHz Single-to-Differential LNA Adopting Wideband $G_text{max}$-Cores Based on Single-Ended Compact Lumped L-C-L and Differential Coupled-Line Embedding Networks 基于单端紧凑型结块 L-C-L 和差分耦合线嵌入网络、采用宽带 $G_text{max}$ 内核的 150-GHz 单变差 LNA

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-10-16 DOI: 10.1109/jssc.2024.3474008

Hokeun Lee, Hyo-Ryeong Jeon, Sang-Gug Lee, Kyung-Sik Choi

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A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration 具有 PAM3 优化 TRX 均衡和 ZQ 校准功能的 16-Gb 37-Gb/s GDDR7 DRAM

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-10-15 DOI: 10.1109/jssc.2024.3472463

Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An, Sang-Hoon Kim, Daewoong Lee, Seongyeal Yang, Se-Mi Kim, Gil-Young Kang, Juseop Park, Kyung-Ho Lee, Hwan-Chul Jung, Gun-Hee Cho, Chan-Yong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sang-Yong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Un-Hak Lim, Hongjun Jin, YoungSeok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn, Won Ju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, Tae-Hoon Park, Changsik Yoo, Tae-Young Oh, SangJoon Hwang

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A 224 Gb/s 3 pJ/bit 40 dB Insertion Loss Transceiver in 3-nm FinFET CMOS 采用 3 纳米 FinFET CMOS 的 224 Gb/s 3 pJ/bit 40 dB 插入损耗收发器

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-10-15 DOI: 10.1109/jssc.2024.3466092

Dirk Pfaff, Muhammad Nummer, Noman Hai, Jingjing Xia, Kai Ge Yang, Mohammad-Mahdi Mohsenpour, Choon-Haw C. H. Leong, Marc-Andre LaCroix, Babak Zamanlooy, Tom Eeckelaert, Dmitry Petrov, Mostafa Haroun, Carson R. Dick, Alif Zaman, Haitao Mei, Tahseen A. Shakir, Carlos Carvalho, Howard Huang, Pratibha Kumari, Ralph Mason, Fahmida Pervin Brishty, Ifrah Jaffri, David A. Yokoyama-Martin

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An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips 用于高级人工智能边缘芯片的整数-浮点双模增益单元内存计算宏程序

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-10-15 DOI: 10.1109/jssc.2024.3470215

Ping-Chun Wu, Win-San Khwa, Jui-Jen Wu, Jian-Wei Su, Chuan-Jia Jhang, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang

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A −90-dBFS-IM3, −164-dBFS/Hz-NSD, 700-MHz-Bandwidth Continuous-Time Pipelined ADC With Digital Cancellation of DAC Errors 具有数字消除 DAC 错误功能的 90 美元-dBFS-IM$_{3}$、164 美元-dBFS/Hz-NSD、700 兆赫带宽连续时间流水线 ADC

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-10-14 DOI: 10.1109/JSSC.2024.3470516

Sharvil Patil;Asha Ganesan;Hajime Shibata;Victor Kozlov;Gerry Taylor;Prawal Shrestha;Zhao Li;Zeynep Lulec;Konstantinos Vasilakopoulos;Raviteja Theertham;Donald Paterson;Qingnan Yu;Aseer Chowdhury

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A 14-b BW /Power Scalable Sensor Interface With a Dynamic Bandgap Reference 具有动态带隙基准的 14-b BW /Power 可扩展传感器接口

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-10-11 DOI: 10.1109/JSSC.2024.3471820

Zhong Tang;Yuyan Liu;Pengpeng Chen;Haining Wang;Xiao-Peng Yu;Kofi A. A. Makinwa;Nick Nianxiong Tan

{"title":"A 14-b BW /Power Scalable Sensor Interface With a Dynamic Bandgap Reference","authors":"Zhong Tang;Yuyan Liu;Pengpeng Chen;Haining Wang;Xiao-Peng Yu;Kofi A. A. Makinwa;Nick Nianxiong Tan","doi":"10.1109/JSSC.2024.3471820","DOIUrl":"10.1109/JSSC.2024.3471820","url":null,"abstract":"This article presents a 14-bit fully dynamic sensor interface that consists of a switched-capacitor (SC) \u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 modulator and a dynamic bandgap reference (BGR). The BGR is implemented by summing the proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) outputs of two PNP-based capacitive DACs. At the sampling rate, the DAC capacitors are pre-charged to the supply and then discharged for a fixed period via PNPs, thus biasing them and simultaneously sampling their base-emitter voltages. By using the modulator’s first integrator to sum the DAC outputs, a dynamic BGR can be realized, which does not need additional reference buffers or decoupling capacitors. To make the system fully dynamic, the modulator itself is based on capacitively biased (CB) floating inverter amplifiers (FIAs). Implemented in a standard 130-nm CMOS process, the sensor interface occupies an area of 0.2 mm2. It achieves an SNDR of >84.5 dB over a scalable bandwidth (BW) ranging from 98 Hz to 5.9 kHz while consuming 1.7–\u0000<inline-formula> <tex-math>$50.8~{mu }$ </tex-math></inline-formula>\u0000W. Furthermore, by employing a time-domain temperature-compensation scheme, it achieves a batch-trimmed gain error of ±0.26% from \u0000<inline-formula> <tex-math>$ - 40~{^{circ } }$ </tex-math></inline-formula>\u0000C to \u0000<inline-formula> <tex-math>$125~{^{circ } }$ </tex-math></inline-formula>\u0000C.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"59 12","pages":"4077-4087"},"PeriodicalIF":4.6,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142415495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Omnidirectional Wireless Power Transfer for Millimetric Magnetoelectric Biomedical Implants 毫米磁电生物医学植入物的全向无线功率传输

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-10-11 DOI: 10.1109/JSSC.2024.3464533

Wei Wang;Zhanghao Yu;Yiwei Zou;Joshua E. Woods;Prahalad Chari;Yumin Su;Jacob T. Robinson;Kaiyuan Yang

{"title":"Omnidirectional Wireless Power Transfer for Millimetric Magnetoelectric Biomedical Implants","authors":"Wei Wang;Zhanghao Yu;Yiwei Zou;Joshua E. Woods;Prahalad Chari;Yumin Su;Jacob T. Robinson;Kaiyuan Yang","doi":"10.1109/JSSC.2024.3464533","DOIUrl":"10.1109/JSSC.2024.3464533","url":null,"abstract":"Miniature bioelectronic implants promise revolutionary therapies for cardiovascular and neurological disorders. Wireless power transfer (WPT) is a significant method for miniaturization, eliminating the need for bulky batteries in today’s devices. Despite successful demonstrations of millimetric battery-free implants in animal models, the robustness and efficiency of WPT are known to degrade significantly under misalignment incurred by body movements, respiration, heart beating, and limited control of implant orientation during surgery. This article presents an omnidirectional WPT platform for millimetric bioelectronic implants, employing the emerging magnetoelectric (ME) WPT modality, and “magnetic field steering” technique based on multiple transmitter (TX) coils. To accurately sense the weak coupling in a miniature implant and adaptively control the multicoil TX array in a closed loop, we develop an active echo (AE) scheme using a tiny coil on the implant. Our prototype comprises a fully integrated 14.2 mm3 implantable stimulator embedding a custom low-power system-on-chip (SoC) powered by an ME film, a TX with a custom three-channel AE RX chip, and a multicoil TX array with mutual inductance cancellation. The AE RX achieves −161 dBm/Hz input-referred noise with 64 dB gain tuning range to reliably sense the AE signal, and offers fast polarity detection for driver control. AE simultaneously enhances the robustness, efficiency, and charging range of ME WPT. Under 90° rotation from the ideal position, our omnidirectional WPT system achieves \u0000<inline-formula> <tex-math>$6.8{ times }$ </tex-math></inline-formula>\u0000 higher power transfer efficiency (PTE) than a single-coil baseline. The tracking error of AE negligibly degrades the PTE by less than 2% from using ideal control.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"59 11","pages":"3599-3611"},"PeriodicalIF":4.6,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142415489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ED-MPIM: An Energy-Efficient Event-Driven Smart Vision SoC With High-Linearity and Reconfigurable MRAM PIM ED-MPIM：采用高线性度和可重构 MRAM PIM 的高能效事件驱动型智能视觉 SoC

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-10-11 DOI: 10.1109/jssc.2024.3470033

Wenao Xie, Haoyang Sang, Beomseok Kwon, Dongseok Im, Sangjin Kim, Sangyeob Kim, Kangho Lee, Hoi-Jun Yoo

引用次数: 0

A Battery-to-3.4 V Hybrid Buck-Boost Converter With Always Reduced Conduction Loss 始终降低传导损耗的电池至 3.4 伏混合降压-升压转换器

IF 5.4 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-10-09 DOI: 10.1109/jssc.2024.3470258

Ji Jin, Yufa Zhou, Changjin Chen, Xu Han, Weiwei Xu, Lin Cheng

引用次数: 0

A 2.08-mW 64.4-dB SNDR 400-MS/s Pipelined- SAR ADC Using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8 nm 使用 8 纳米耐失配和 PVT 变化动态偏置环形放大器的 2.08 mW 64.4-dB SNDR 400-MS/s 流水线 SAR ADC

IF 4.6 1区工程技术

IEEE Journal of Solid-state Circuits Pub Date : 2024-10-09 DOI: 10.1109/JSSC.2024.3471915

Yong Lim;Jaehoon Lee;Jongmi Lee;Kwangmin Lim;Seunghyun Oh;Jongwoo Lee

{"title":"A 2.08-mW 64.4-dB SNDR 400-MS/s Pipelined- SAR ADC Using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8 nm","authors":"Yong Lim;Jaehoon Lee;Jongmi Lee;Kwangmin Lim;Seunghyun Oh;Jongwoo Lee","doi":"10.1109/JSSC.2024.3471915","DOIUrl":"10.1109/JSSC.2024.3471915","url":null,"abstract":"In this article, we introduce a new dynamically biased ring amplifier that is tolerant to mismatch and PVT variation without requiring bias calibration, and we verify it in a 12-bit 400-MS/s pipelined-SAR analog-to-digital converter (ADC), fabricated in an 8-nm FinFET process. Our novel ring amplifier solves the biasing issues inherent in conventional ring amplifiers while maintaining the benefits of high gain, slew-based charging, and nearly rail-to-rail output swing. We also propose a technique to enhance the DC accuracy of a switched-capacitor common-mode feedback (CMFB) without consuming additional power, which we named feedback voltage sampling CMFB. Furthermore, we introduce a full-scale matching residue amplification technique for the prototype pipelined-SAR ADC to utilize the top-plate input sampling for the first-stage SAR ADC, resulting in faster and lower power conversion. The prototype ADC demonstrates the robustness of our dynamically biased ring amplifier to mismatch and PVT variation without any interstage gain, bias, or reference calibration, and achieves 64.4-dB SNDR and 77.6-dB SFDR for a low-frequency input while consuming 2.08 mW. This measured performance is equivalent to Walden and Schreier FoMs of 3.8 fJ/conversion\u0000<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>\u0000step and 174.2 dB, respectively.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"59 12","pages":"4199-4210"},"PeriodicalIF":4.6,"publicationDate":"2024-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142397732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0