IEEE Journal of Emerging and Selected Topics in Power Electronics最新文献_第8页

A Fully-Integrated CMOS Gate Driver for a GaN-Based Half-Bridge in 48/12 V Bidirectional Automotive Power Conversion 基于gan的半桥式48V/12V双向汽车电源转换全集成CMOS栅极驱动器

IF 5.7 2区工程技术

IEEE Journal of Emerging and Selected Topics in Power Electronics Pub Date : 2026-10-01 Epub Date: 2026-03-29 DOI: 10.1109/JESTPE.2026.3698099

Xinyi Li;Siqin Hua;Yuanchi Cai;Yuan Gao

{"title":"A Fully-Integrated CMOS Gate Driver for a GaN-Based Half-Bridge in 48/12 V Bidirectional Automotive Power Conversion","authors":"Xinyi Li;Siqin Hua;Yuanchi Cai;Yuan Gao","doi":"10.1109/JESTPE.2026.3698099","DOIUrl":"10.1109/JESTPE.2026.3698099","url":null,"abstract":"Bidirectional DC/DC converters are essential for efficient power distribution in electric vehicles. Gallium nitride (GaN) devices enable high power density as switching elements, but their intrinsic characteristics impose stringent requirements on the reliability of GaN drivers. This article proposes a fully-integrated half-bridge GaN driver, which enables bidirectional power transfer between 12 and 48 V systems. A three-level/bipolar GaN gate driver enhances system reliability under high dv/dt conditions. The integrated charge-sharing bootstrap circuit achieves a compact design and reliable operation of the high-side device. The adaptive dead-time modulation provides an adjustable delay under different load conditions to minimize the dead-time loss. The proposed GaN driver is fabricated in a <inline-formula> <tex-math>$0.18~mu $ </tex-math></inline-formula>m BCD process with a die area of 3.654 mm2. Design considerations in the layout and printed circuit board (PCB) implementation are discussed. Measurement results demonstrate that at a 5 MHz operating frequency, the driver achieves bidirectional conversion between 12 and 48 V. The peak efficiencies are 94.6% for the 18-to-12 V conversion and 94.18% for the 12-to-18 V conversion. Experimental results show that the design can achieve a maximum output power of 22.12 W in buck mode and 22.06 W in boost mode.","PeriodicalId":13093,"journal":{"name":"IEEE Journal of Emerging and Selected Topics in Power Electronics","volume":"14 5","pages":"6056-6067"},"PeriodicalIF":5.7,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148290667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Supervisory Voltage Control Based on Reinforcement Learning for DC–DC Buck Converters With Constant Power Loads 基于强化学习的恒负荷DC-DC降压变换器电压监控

IF 5.7 2区工程技术

IEEE Journal of Emerging and Selected Topics in Power Electronics Pub Date : 2026-10-01 Epub Date: 2026-07-01 DOI: 10.1109/JESTPE.2026.3709244

Shima Shahnooshi;Javad Ebrahimi;Alireza Bakhshai

{"title":"Supervisory Voltage Control Based on Reinforcement Learning for DC–DC Buck Converters With Constant Power Loads","authors":"Shima Shahnooshi;Javad Ebrahimi;Alireza Bakhshai","doi":"10.1109/JESTPE.2026.3709244","DOIUrl":"10.1109/JESTPE.2026.3709244","url":null,"abstract":"This article proposes a supervisory voltage control framework for DC–DC converters in DC microgrids application supplying constant power loads (CPLs), which are known to introduce negative impedance characteristics that compromise system stability. The proposed framework operates with a cascaded PI controller during normal conditions and seamlessly switches to a transient-prioritized twin-delayed deep deterministic policy gradient (TD3)-based controller during dynamic events, avoiding full reliance on model-free deep reinforcement learning (DRL) and enhancing reliability in steady-state operation. A hysteresis-based supervisory mechanism is proposed to coordinate the transition between DRL-based control and classic control according to the system’s operating condition. This supervisory logic relies on the moving average of DC-link voltage deviations to trigger smooth and robust transitions between control modes, preventing unnecessary transitions and maintaining stability under a wide range of disturbances. In parallel, a transient-aware reward function is designed, embedding hysteresis-triggered shaping terms to explicitly prioritize fast error reduction during large transients while preserving damping and stability near steady state. Simulations in MATLAB/Simulink as well as hardware-in-the-loop (HIL) experiments on the OPAL-RT platform are conducted to validate the effectiveness of the proposed control method.","PeriodicalId":13093,"journal":{"name":"IEEE Journal of Emerging and Selected Topics in Power Electronics","volume":"14 5","pages":"6345-6358"},"PeriodicalIF":5.7,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148371890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Droop-Controlled Microgrid Using Intelligent Presynchronization for Grid Connection 基于智能预同步的下垂控制微电网并网

IF 5.7 2区工程技术

IEEE Journal of Emerging and Selected Topics in Power Electronics Pub Date : 2026-10-01 Epub Date: 2026-07-13 DOI: 10.1109/JESTPE.2026.3712354

Faa-Jeng Lin;Kuang-Hsiung Tan;Chun-Ting Lin;Chen-Yi Wang;Wen-Kuei Wei

{"title":"Droop-Controlled Microgrid Using Intelligent Presynchronization for Grid Connection","authors":"Faa-Jeng Lin;Kuang-Hsiung Tan;Chun-Ting Lin;Chen-Yi Wang;Wen-Kuei Wei","doi":"10.1109/JESTPE.2026.3712354","DOIUrl":"10.1109/JESTPE.2026.3712354","url":null,"abstract":"In this study, a novel presynchronization method is proposed for a droop-controlled microgrid to achieve grid connection. When the microgrid operates in islanded mode and intends to reconnect to the power grid, a seamless transition between islanded mode and grid-connected mode is challenging because of phase, frequency, and voltage mismatches. If the microgrid is not synchronized with the power grid, inrush currents and voltage fluctuations may lead to system instability and damage equipment during grid connection. Hence, a novel presynchronization method is proposed to achieve phase synchronization, frequency, and voltage restoration for the droop-controlled microgrid. Moreover, two binarized probabilistic Legendre fuzzy neural network (BPLFNN) controllers are proposed to replace the traditional proportional–integral (PI), PI-derivative neural network (PIDNN), and fuzzy neural network (FNN) controllers for frequency and voltage restoration. Finally, the effectiveness of the proposed BPLFNN-based presynchronization method to rapidly achieve grid connection is verified by experimentation. The voltage and frequency restoration times are significantly reduced to 0.72 and 0.66 s, which are superior to the PI controllers (1.14 and 1.55 s), PIDNN controllers (1.06 and 1.18 s), and FNN controllers (0.91 and 1.04 s).","PeriodicalId":13093,"journal":{"name":"IEEE Journal of Emerging and Selected Topics in Power Electronics","volume":"14 5","pages":"6639-6656"},"PeriodicalIF":5.7,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148432272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Model Vectorization and Low-Fluctuation Method for Dynamic Wireless Power Transfer 动态无线电力传输的模型矢量化和低波动方法

IF 5.7 2区工程技术

IEEE Journal of Emerging and Selected Topics in Power Electronics Pub Date : 2026-10-01 Epub Date: 2026-03-04 DOI: 10.1109/JESTPE.2026.3689746

Xiaoning Li;Yuxi Gu;Fei Xu;Xian Zhang

{"title":"Model Vectorization and Low-Fluctuation Method for Dynamic Wireless Power Transfer","authors":"Xiaoning Li;Yuxi Gu;Fei Xu;Xian Zhang","doi":"10.1109/JESTPE.2026.3689746","DOIUrl":"10.1109/JESTPE.2026.3689746","url":null,"abstract":"Dynamic wireless power transfer (DWPT) is a pivotal technology for future mobile electrical energy interaction. However, its widespread adoption is challenged by significant transfer fluctuations induced by spatial and temporal factors. This article proposes a vectorization method of variables to reconstruct the controlled scalar variables into space vector variables for analyzing fluctuations in both spatial and temporal factors. A vector-based model is further established for the multiple-transmitter (Tx)–single-receiver (Rx) DWPT system. To improve the performance, the model is constrained and ultimately simplified into a single-Tx–single-Rx model. Based on this model, a stable output of the Rx is achieved just by maintaining the amplitude of the input voltage vector, which can track the Rx position synchronously. This article further investigates the impact of the coil design parameters on the electrical parameters, cross-coupling, fundamental content, and offset of coupling coefficient curves, which can impact the model and system performance through the analysis. Compared with two existing advanced methods, the proposed approach demonstrates superior performance in experiments: power fluctuations remain around ±1.2% across all tested positions, and average efficiency exceeds 90%, peaking at 92.3%.","PeriodicalId":13093,"journal":{"name":"IEEE Journal of Emerging and Selected Topics in Power Electronics","volume":"14 5","pages":"6854-6868"},"PeriodicalIF":5.7,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149091408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Variable-Reference Discontinuous Pulse Width Modulation Method for Four-Level Neutral-Point-Clamped Inverters 四电平中性点箝位逆变器的变参考断续脉宽调制方法

IF 5.7 2区工程技术

IEEE Journal of Emerging and Selected Topics in Power Electronics Pub Date : 2026-10-01 Epub Date: 2026-03-12 DOI: 10.1109/JESTPE.2026.3691797

Yu Wang;Jianfei Chen;Mengyuan Wang;Chengzhi Li;Jiaqi Chi;Hongda Li

{"title":"Variable-Reference Discontinuous Pulse Width Modulation Method for Four-Level Neutral-Point-Clamped Inverters","authors":"Yu Wang;Jianfei Chen;Mengyuan Wang;Chengzhi Li;Jiaqi Chi;Hongda Li","doi":"10.1109/JESTPE.2026.3691797","DOIUrl":"https://doi.org/10.1109/JESTPE.2026.3691797","url":null,"abstract":"Four-level neutral-point-clamped (4L-NPC) inverters are widely used in low- and medium-voltage applications. However, existing variable-reference pulse width modulation (VRPWM) and carrier-overlapped PWM (COPWM) methods often lead to increased switching losses and uneven loss distribution among power devices. To address this issue, this article proposes a unified variable-reference discontinuous PWM (VRDPWM) framework that enables two clamping modes: full-clamping VRDPWM-I method and partial-clamping VRDPWM-II method. In the full-clamping method, the phase leg is clamped to the DC-link voltage levels during the discontinuous interval, thereby reducing the number of switching transitions. In contrast, the partial-clamping method selectively suppresses the switching activity of the inner switch pair to redistribute switching losses by exploiting the switching redundancies of the 4L-NPC topology. Furthermore, the influence of different clamping states on capacitor voltage dynamics is analytically investigated, and a compatible capacitor voltage-balancing method is developed. The experimental and simulation results verify that the proposed VRDPWM-II method effectively reduces the switching loss of the inner switch pair while maintaining high output current quality and stable DC-link capacitor voltages.","PeriodicalId":13093,"journal":{"name":"IEEE Journal of Emerging and Selected Topics in Power Electronics","volume":"14 5","pages":"6287-6303"},"PeriodicalIF":5.7,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149096990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Passivity-Oriented Analysis of Control Delay on Output Admittance Beyond the Nyquist Frequency of Grid-Following Inverters 电网跟随逆变器输出导纳超过奈奎斯特频率控制延迟的无源分析

IF 5.7 2区工程技术

IEEE Journal of Emerging and Selected Topics in Power Electronics Pub Date : 2026-10-01 Epub Date: 2026-03-11 DOI: 10.1109/JESTPE.2026.3691821

Yukai Huang;Jing Duan;Songtao Huang;Jie Ye;Zhixiong Zhang;Jinbang Xu;Anwen Shen;Yihua Hu

{"title":"Passivity-Oriented Analysis of Control Delay on Output Admittance Beyond the Nyquist Frequency of Grid-Following Inverters","authors":"Yukai Huang;Jing Duan;Songtao Huang;Jie Ye;Zhixiong Zhang;Jinbang Xu;Anwen Shen;Yihua Hu","doi":"10.1109/JESTPE.2026.3691821","DOIUrl":"https://doi.org/10.1109/JESTPE.2026.3691821","url":null,"abstract":"The interconnection stability of grid-connected inverters can be evaluated through the dissipative characteristics of the output admittance. While the influence of admittance components beyond the Nyquist frequency (NF) on stability has been recognized, the effects of control delays on high-frequency admittance behavior still merit further investigation. A detailed analysis of output admittance is presented, considering two primary delay sources: the system sampling period and the sampling instant. The absolute delay defined by the sampling frequency is quantitatively assessed, and the relative delay caused by the sampling instant affects both the depth and the span of the negative damping region. The results indicate that although increasing the sampling frequency mitigates nonpassive admittance effects above the NF, nonpassivity remains a key contributor to high-frequency instability. To address this issue, an admittance-based passive damping method is developed based on an admittance model that includes frequency aliasing effects to improve high-frequency stability. The experimental results validate the theoretical analysis and demonstrate the effectiveness of the proposed method.","PeriodicalId":13093,"journal":{"name":"IEEE Journal of Emerging and Selected Topics in Power Electronics","volume":"14 5","pages":"5732-5745"},"PeriodicalIF":5.7,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149097187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Modeling and Analysis of Operating Limits of the Differential Boost Inverter 差动升压逆变器工作极限的建模与分析

IF 5.7 2区工程技术

IEEE Journal of Emerging and Selected Topics in Power Electronics Pub Date : 2026-10-01 Epub Date: 2026-03-25 DOI: 10.1109/JESTPE.2026.3696702

Diana Lopez-Caiza;Marcelo A. Perez;Felipe Ruiz;Samir Kouro;Frede Blaabjerg

{"title":"Modeling and Analysis of Operating Limits of the Differential Boost Inverter","authors":"Diana Lopez-Caiza;Marcelo A. Perez;Felipe Ruiz;Samir Kouro;Frede Blaabjerg","doi":"10.1109/JESTPE.2026.3696702","DOIUrl":"https://doi.org/10.1109/JESTPE.2026.3696702","url":null,"abstract":"The differential boost inverter (DBI) is a single-stage step-up topology composed of two bidirectional boost converters whose outputs are connected in differential mode to generate an AC output voltage. The DBI poses significant modeling challenges, since all variables operate with both DC and AC components, requiring a highly complex dynamical model to accurately capture its behavior. Also, the operating range of this converter is restricted both in the modulation indexes, which are limited to the interval between 0 and 1, and in the capacitor voltage, which must always be above the input voltage. In addition, a large harmonic content in the converter variables when working at certain operating points can increase the total harmonic distortion (THD), degrading the performance. This work presents a model that considers both the DC and fundamental AC components of the converter variables. Based on this model, the allowable operating ranges for the modulation indexes and capacitor voltages are defined. Furthermore, the model is extended to determine the harmonic content of the capacitor voltage, enabling the identification of the operating ranges in which a low THD is achieved. The proposed analysis introduces a flexible DC component in the modulation, without assuming a fixed DC bias, which broadens the valid operating region and enhances the potential for THD minimization. Finally, a DBI prototype has been built to validate the model and analysis, with experimental results confirming the mathematical relationships at representative operating points.","PeriodicalId":13093,"journal":{"name":"IEEE Journal of Emerging and Selected Topics in Power Electronics","volume":"14 5","pages":"5974-5984"},"PeriodicalIF":5.7,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"149097915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Non-linear Discrete Time Model-based Hybrid Super Twisting SMC of a 1.5 MHz DAB Converter 基于非线性离散时间模型的1.5 MHz DAB变换器混合超扭SMC

IF 5.5 2区工程技术

IEEE Journal of Emerging and Selected Topics in Power Electronics Pub Date : 2026-10-01 DOI: 10.1109/jestpe.2026.3739175

Naveed Ishraq, Changkyu Bai, Saikat Dey, Writtik Dutta, Vivek Thomas Chacko, Ian Willows, Sritharini Radhakrishnan, Raja Ayyanar, Mike Ranjram, Ayan Mallik

引用次数: 0

Digital Slope Compensation Framework for Achieving Robust Frequency and Voltage Regulation in Ripple-Controlled Buck Converters With Very Low-ESR Output Capacitors 在极低esr输出电容的纹波控制降压变换器中实现鲁棒频率和电压调节的数字斜率补偿框架

IF 5.7 2区工程技术

IEEE Journal of Emerging and Selected Topics in Power Electronics Pub Date : 2026-10-01 Epub Date: 2026-03-25 DOI: 10.1109/JESTPE.2026.3677422

Yu-Hsuan Chen;Le-Ren Chang-Chien;Chun-Hsun Wu

{"title":"Digital Slope Compensation Framework for Achieving Robust Frequency and Voltage Regulation in Ripple-Controlled Buck Converters With Very Low-ESR Output Capacitors","authors":"Yu-Hsuan Chen;Le-Ren Chang-Chien;Chun-Hsun Wu","doi":"10.1109/JESTPE.2026.3677422","DOIUrl":"10.1109/JESTPE.2026.3677422","url":null,"abstract":"This article presents a ripple-controlled buck converter with fully digital slope-compensation technique to achieve adaptive voltage and frequency regulation. The unique advantage of the proposed digital slope-compensation framework lies in its ability to adaptively adjust the compensation slope, which can be effectively applied to overcome the major challenges of ripple-based control, including voltage stability with low-equivalent series resistance (ESR) output capacitors, voltage quality (offset and ripple), switching-frequency variation, and slow transient response. As such, the framework provides a comprehensive control solution that overcomes the key limitations inherent to ripple-based control. The proposed digital control was implemented in a buck converter with input and output voltages set at 4.2 and 1.2 V, respectively, using an output capacitor with an ESR of only 5 m<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>. Experimental testing encompassed a load current variation range spanning from 100 to 800 mA. Results demonstrate exceptional stability in switching frequency, exhibiting a mere 0.2% variation (1.49 kHz/A). The voltage offset is minimized to 1.25%. Furthermore, the transient acceleration significantly reduces both rising and falling transient responses from <inline-formula> <tex-math>$20~mu $ </tex-math></inline-formula>s to within <inline-formula> <tex-math>$10~mu $ </tex-math></inline-formula>s, while concurrently decreasing overshoot and undershoot voltages by 42% and 34%, respectively.","PeriodicalId":13093,"journal":{"name":"IEEE Journal of Emerging and Selected Topics in Power Electronics","volume":"14 5","pages":"6170-6181"},"PeriodicalIF":5.7,"publicationDate":"2026-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147507700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Time-Varying Period Two-Third Pulsewidth Modulation Scheme for Current Source Inverters in Discontinuous Conduction Mode 断续导通模式下电流源逆变器的时变周期三分之二脉宽调制方案

IF 5.7 2区工程技术

IEEE Journal of Emerging and Selected Topics in Power Electronics Pub Date : 2026-10-01 Epub Date: 2026-03-09 DOI: 10.1109/JESTPE.2026.3672143

Baoxuan Chen;Yao Sun;Shiming Xie;Wenjing Xiong;Jiawei Tan

引用次数: 0