{"title":"JIT manufacturing in a highly complex, low volume capital equipment business","authors":"M.P. Niven, M. F. Werner","doi":"10.1109/IEMT.1991.279764","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279764","url":null,"abstract":"The implementation of JIT (just-in-time) manufacturing is described. It is concluded that JIT required a fundamental change in the company's business philosophy. It requires time, commitment, and belief in the value of its basic concepts. It is not a quick fix, an inventory reduction scheme or a way to have suppliers hold one's inventory. With a patient approach and dedicated teams, it has produced a major change in the company's process.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115720924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"IBM Austin Electronic Card Assembly and Test six sigma process modeling strategy","authors":"S. Mulligan, R. Jereb, B.E. Luhning","doi":"10.1109/IEMT.1991.279757","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279757","url":null,"abstract":"The authors summarize the IBM Austin Electronic Card Assembly and Test (ECAT) process modeling strategy that is being used to develop a six sigma ECAT manufacturing process. Specifically, the strategy calls for each process center to determine through a series of designed experiments what incoming, outgoing, and internal process and product variables need to be controlled in order for ECAT to reach six sigma process capability. The authors discuss how the strategy was implemented, the progress that occurred in 1990, and the level for 1991.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126989619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. H. Law, C. Mattoe, J. Thomson, T. Smith, R. Zappula
{"title":"Robust-design of a metallization process for ceramic substrates","authors":"H. H. Law, C. Mattoe, J. Thomson, T. Smith, R. Zappula","doi":"10.1109/IEMT.1991.279819","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279819","url":null,"abstract":"The electroless nickel deposition process on ceramic substrates was optimized using a Taguchi-based robust-design method. The plating parameter settings were obtained in only 27 experiments. The savings in experiments is significant when compared to a full factorial design of 486 runs. The yield of completely metallized substrate was increased substantially. Under the optimal conditions, a 100% yield was obtained in the confirmation run of 80 ceramic samples.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130447597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Wire bonding limitations for high density fine pitch plastic packages","authors":"A. Saboui","doi":"10.1109/IEMT.1991.279750","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279750","url":null,"abstract":"The limits of process capability for fine pitch high density packages are shown. By the help of a special design test die and a PQFP (plastic quad flat package) frame, three different wire diameters with different lengths were bonded, molded, analyzed, and compared. Different ball sizes with special design capillary were made and measured. These measurements were used to study the ball size deformation before and after bonding. How a correct bonded ball should look and what size initial ball diameter must be chosen for each wire diameter and pad are also discussed. The effects of loop-height on pad pitch reduction and an improved loop structure are also examined. In addition, attention is given to what is the minimum pad size for today's technology for different wire diameter, how a minimum pad size should be calculated, what is the minimum and maximum wire length and loop height which the existing wirebonders are capable of bonding, what are the molding limits, and what are the wire deflection limits.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115953151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An AI-based manufacturing design rule checker and path optimizer for PCB production preparation and manufacturing","authors":"A. Hidde, A. Gierse","doi":"10.1109/IEMT.1991.279787","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279787","url":null,"abstract":"The authors discuss printed circuit board (PCB) manufacturing design rule checking (MDRC) in combination with the path optimizing of the assembly process in a heterogeneous, distributed, and networked information system environment linked with databases in a defined factory infrastructure. An increase in the degree of automation requires greater continuity of information flow starting with the customer order through to the sensor and actuator layer of manufacturing machinery. After the presentation of information infrastructure models such as the hierarchical production control system and the Y-model, the manufacturing design system (MDS) for the production preparation environment is derived which contains also the manufacturing design rule checking and path optimizing applicable to the PCB assembly process. In particular, the linkage between the design rule checking and the path optimizing process via the hierarchical two-phase cross-linked unit formation method based on technical and strategic characteristics is considered. The assembly process of a PCB with different components is cited as an example. The software package is written in the artificial-language Common LISP with the dialect SCHEME.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"102 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113993796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Laser-induced, plasma-based, non-contact electrical testing of functional hardware","authors":"D. Millard, R. Block, Karl Umstader","doi":"10.1109/IEMT.1991.279780","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279780","url":null,"abstract":"In order to non-destructively test fine-pitch devices, a system has been developed that uses a laser-induced plasma to provide the conduction between an electronic component and monitoring equipment. This non-contact system has been shown to produce a 10-20- mu s non-loading electrical pathway that can transmit both DC and high-frequency signals to or from a printed wiring board. The non-contact electrical pathway is first expected to be used for probing and observation of electronic equipment.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116608516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"LEAPFROG-a manufacturing and EHS partnership","authors":"J. R. Jewett","doi":"10.1109/IEMT.1991.279800","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279800","url":null,"abstract":"LEAPFROG is the title of a program at Intel Corporation which addresses concerns about hazardous chemicals in semiconductor manufacturing processes by dealing with them at the emerging technology stage. One aspect of the program is to incorporate environmental, health, and safety (EHS) design parameters into each new technology development plan. The goal is for each resulting process to have minimal EHS risk due to chemical use. Another aspect of LEAPFROG targets specific hazardous chemicals in existing processes, and endeavors to mitigate these problems through development of process alternatives. The author discusses the program structure, implementation, and some resulting experiences from an environmental perspective.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"305 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115243244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Inert gas wave soldering evaluation","authors":"J.E. Altpeter, L. L. Kneisel, J. Baker","doi":"10.1109/IEMT.1991.279798","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279798","url":null,"abstract":"Production modules were soldered using adipic acid/isopropanol as a flux and atomized formic acid to further enhance oxide reduction over the molten soldered module. The objectives of the evaluation were to assess system capability, measurable performance versus conventional wave soldering equipment performance, and environmental impact. The system capability for overall machine performance, from belt speeds to repeatable solder heights and solder joints, has demonstrated the effectiveness of inert gas soldering over current conventional soldering technology. The inert gas system performance versus conventional process performance using production level product has demonstrated the feasibility the system has for production implementation by lowering the solder defect rate by a fourfold improvement. The positive environmental impact of inert gas soldering consists in reductions in volatile organic compounds, lead, and chlorofluorocarbon (CFC) emissions. Cost comparison of inert gas soldering to conventional wave solder systems is very favorable when total costs of the cleaning machines with CFCs and floor space are compared.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123271125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A tin based TAB assembly process","authors":"D. Field","doi":"10.1109/IEMT.1991.279740","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279740","url":null,"abstract":"The feasibility of using a TinCap TAB (tape automated bonding) ILB (inner lead bond) structure to provide a strong ILB connection has been demonstrated. The project investigated placing a pad of tin on top of a gold TAB bump as part of the wafer fabrication process. The tin is then used to form a reflowed ILB joint with a gold-plated tape lead. This gold/tin bond should provide a strong joint while avoiding some of the problems associated with tin-plated TAB tape. This TAB bond is referred to as the TinCap ILB structure. The process development work included modifications to the current TAB photoresist imaging process, development of a tin plating capability, and formulation of a suitable etch chemistry for a tin/gold bump. An inner lead bonding process was developed through evaluating and testing of two separate bonding systems. A substantial reliability evaluation involving over 200 live devices was carried out to determine the suitability of this interconnect for future products.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115120842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Effects of RCA claning upon breakdown voltages of thin gate oxides","authors":"C. C. Johnson, K. Kurtz, J. Prince","doi":"10.1109/IEMT.1991.279818","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279818","url":null,"abstract":"The authors investigated the effects of pre and post-oxidation RCA cleaning on thin oxides using breakdown voltages at current densities of 100 mu A/cm/sup 2/ and 100 mA/cm/sup 2/. The RCA clean consisted of SC1 (NH/sub 4/OH in water and H/sub 2/O/sub 2/), a dilute HF dip and SC2 (HCl in water and H/sub 2/O/sub 2/). Three experiments were performed to test the effect of each step of the pre- and post-oxidation cleans, the effect of the order in which the steps of the clean were performed, and the effect of the age of the solutions. HF was found to decrease oxide thickness without increasing the number of fails. In the post-oxidation clean, SC2 increased the number of failing oxides, but this effect was alleviated if SC1 was performed beforehand. This and other data led to the conclusion that SC2 was selectively etching the oxide. In addition, an experiment dealing with holding time of the solutions (0-12 h) was performed, but the results were not conclusive.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130414133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}