{"title":"Cost saving opportunities with multi-chip modules","authors":"J. Mavroides","doi":"10.1109/IEMT.1991.279826","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279826","url":null,"abstract":"The author describes an MCM (multi-chip module) application that was driven by cost. A study of MCM technologies focused on the MCM assembly and interconnect to the motherboard. Models were developed to calculate the assembly and test costs for MCMs using wirebond and tape automated bonding technologies. Another model was used to evaluate interconnect options, both separable and nonseparable (e.g., soldered). The cost analysis verified that significant cost savings could be achieved by using MCM technology and, along with a technical evaluation of the alternatives, led to an MCM physical design for this application.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134371681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Effects of skewing CMOS output driver switching on the 'simultaneous' switching noise","authors":"R. Senthinathan, J. Prince, S. Nimmagadda","doi":"10.1109/IEMT.1991.279810","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279810","url":null,"abstract":"A detailed study of the characteristics of CMOS receiver noise immunity and the effects of skewing CMOS output drives on simultaneous switching noise was performed. Closed-form equations are given to calculate the simultaneous switching noise and the number of V/sub DD//V/sub SS/ bond pads-package pins in multichip modules. Guidelines for grouping and optimal skewing of CMOS output drivers to reduce the total effective power/ground noise are discussed. Performance trade-offs in using an additional damping resistor in the output driver circuit to reduce power/ground noise were analyzed. Design curves are given to minimize the effective switching noise without much trade-off in output driver speed.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116095951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Recognition of pattern defects of printed circuit board using topological information","authors":"M. Ito, Y. Nikaido","doi":"10.1109/IEMT.1991.279777","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279777","url":null,"abstract":"The authors discuss an optical inspection system in which topological information on conductors and insulators of PCBs (printed circuit boards) is used for the detection of defects. The conventional image comparison methods, such as direct comparison of two images and image expansion-contraction for a design-rule inspection, have some difficulties in finding large defects, missing patterns, and a short. To cope with these problems, topological information on PCBs is introduced in this proposed method. This will also make it easy to access computer-aided design data for the inspection process. The principle of the system is mainly based on the topological comparison method which compares the inspection graph obtained from the skeletons of the conductor and insulator images of an inspection PCB with those of the standard or reference board. Topological information incorporates weighted graphs composed of several types of nodes and edges, connections, and their locations. Both conductor and insulator graphs have such information.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121842100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High density interconnect verification of unpopulated multichip modules","authors":"O. Woodard","doi":"10.1109/IEMT.1991.279832","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279832","url":null,"abstract":"Six methods of interconnect verification are discussed. Three are methods in general use for printed circuit applications and are becoming available for the higher resolution requirements of MCM (multichip module) substrates. Flying probe resistance testing is a direct, reliable test method but throughputs are too low for complex MCM substrates. Bed-of-nails (BON) resistance testers can be used for high-speed testing at the expense of high fixturing costs. Flying probe capacitance testers provide high throughputs but are less reliable than resistance testers. Flying probe combined resistance-capacitance testers have high throughputs with more reliable results. Two emerging technologies have been demonstrated to have some advantages over existing methods. Glow discharge testing is more reliable than capacitive testing and has much higher throughput. Voltage contrast electron beam (VCEB) testing has very high resolution and has ten times the throughput of any other electrical test method. VCEB is noncontact and nondamaging, allowing it to be used for in-process testing.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126139120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The latest molding technology for fine pitch P-QFP","authors":"Y. Noda","doi":"10.1109/IEMT.1991.279752","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279752","url":null,"abstract":"The author describes the molding technology for fine pitch P-QFP. Problems associated with the packaging technology for fine pitch P-QFP are discussed with reference to the best directions for package structure concerning larger package, larger IC chips, thinner package, and fine lead pitch package; molding methods; and the questions of what kind of a molding compound can satisfy the above mentioned molding demands and what are the material's physical and chemical properties and characteristics? The package structure, a new molding method, and a new molding compound are described.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126184364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Reuss, T. Sparks, S. Cosentino, J. Ford, T. Hulseweh, J. Hoskins, V. Lam, J. Barden, M. Granum
{"title":"Introduction of BiCMOS into a production CMOS facility","authors":"R. Reuss, T. Sparks, S. Cosentino, J. Ford, T. Hulseweh, J. Hoskins, V. Lam, J. Barden, M. Granum","doi":"10.1109/IEMT.1991.279746","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279746","url":null,"abstract":"A unique set of circumstances is required for the rapid introduction of a 1- mu m BiCMOS capability from R&D into a CMOS production facility. Not only was the lead time very short, but the wafer size and equipment sets were not compatible and the main thrust/experience of the personnel was different. The authors review the proposed novel solution, organizational details, technical approach, and accomplishments of this process transfer. The solution was to redefine the process using much of the existing production CMOS technology as a baseline and add additional features as required to generate a BiCMOS process. The criterion for transfer was not to reproduce certain sheet resistances, etch profiles, and diffusion cycles, but rather to achieve the same device electrical parameters. This decision allowed the designers to begin their work in earnest because they had a firm of model parameters for circuit simulations. Because much of the process was already well-established CMOS technology and the module development experiments resolved key BiCMOS unknowns, the first full flow process integration lots resulted in good yields of 64K CMOS and BiCMOS SRAMs.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"50 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130910323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High density interconnect verification using voltage contrast electron beam","authors":"A. W. Ross, R.R. Goruganthu, O.C. Woodard","doi":"10.1109/IEMT.1991.279793","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279793","url":null,"abstract":"High reliability testing of multi-chip module (MCM) substrates has been demonstrated using voltage contrast electron beam (VCEB) open-shorts testing. Features as small as 100 mu m are probed over an area of 10 cm*10 cm in a tool developed by installing high-precision digital electronics and a novel large field of view secondary electron analyzer into a conventional scanning electron microscope. These modifications in conjunction with sophisticated calibration and data analysis techniques have produced the research tool which is now routinely used to test substrates fabricated at Microelectronics and Computer Technology Corporation (MCC) as well as many fabricated by MCC's shareholders. The performance of the system was assessed by testing MCM product substrates and special test substrates. Various combinations of conductors and insulators were tested. The test targets were designed with numerous feature sizes over the entire field of view so that probing accuracy and test uniformity could be characterized.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114163685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Environmentally conscious products","authors":"W.J. Brady","doi":"10.1109/IEMT.1991.279795","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279795","url":null,"abstract":"IBM's environmental policy and IBM's initial criteria for environmentally conscious products are discussed. The main concept considered is that of a manufacturing loop in which products are made of recyclable materials and designed to be easily taken apart to be reused or recycled again. The tighter that loop, the less worrisome is the waste that will be generated.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123857568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Ceramic packages and substrates prepared by electroless Ni-Au process","authors":"M. Nakazawa, S. Wakabayashi","doi":"10.1109/IEMT.1991.279816","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279816","url":null,"abstract":"An electroless nickel-gold plating process for thin and thick film high-density ceramic packages and substrates was investigated. A highly selective electroless nickel process using immersion gold activation was developed. Activation for the electroless nickel plating using an immersion gold solution improved the deposition selectivity on conductor patterns whose width is narrower than 100 mu m. The thickness of the electroless nickel must be over 4.5 mu m to prevent heat discoloration of the gold surface. The dipping time of immersion gold plating on nickel must be shorter than 4 min to obtain good adhesion. An electroless gold plating solution and process were developed. The gold solution was basically composed of KAu(CN)/sub 2/ DMAB, and Sorensen buffer solution. Stabilizer masks nickel contamination and prevents the solution from decomposition. This solution has improved the following properties: poor adhesion to electroless nickel, low deposition rate, poor selectivity, short working lives, and bath instability. This electroless process makes it possible to match the characteristic impedance of signal lines on packages and substrates with the designed value.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116600927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"TARGET: thermal accelerated reliability go-no-go environmental testing dynamic board thermal shock using a single liquid fluorocarbon bath","authors":"B.P. Beaton","doi":"10.1109/IEMT.1991.279779","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279779","url":null,"abstract":"TARGET, a novel method of accelerated thermal stress for board testing, is described. This method utilizes Fluorinert as the medium for rapid thermal energy transfer. Possible applications include environments for STRIFE testing and board debug. One of the most promising applications is in-line environmental stress screening (ESS). Boards receive a thorough temperature stress screen in the time taken for conventional go-no-go tests. The process is described in detail and analyzed. Data from initial experiments are presented.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"237 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122711656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}