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2018 IEEE East-West Design & Test Symposium (EWDTS)最新文献

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The Deterministic-Statistical Model of a MIMO System Signal Propagation Indoors 室内MIMO系统信号传播的确定性统计模型
2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524603
A. A. Vaganova, N. N. Kisel, A. I. Panychev
{"title":"The Deterministic-Statistical Model of a MIMO System Signal Propagation Indoors","authors":"A. A. Vaganova, N. N. Kisel, A. I. Panychev","doi":"10.1109/EWDTS.2018.8524603","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524603","url":null,"abstract":"A deterministic-statistical model for the analysis of signal propagation indoor is proposed. The model is based on a combination of the deterministic three-dimensional ray tracing method and the statistical account of the changing spatial structure of the communication channels and the irregularities of the reflecting surfaces. The channel matrix elements of the MIMO system are estimated based on the proposed model.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121209638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Development of Compact Coupler Devices on Microstrip Structures with Different Substrate Thicknesses 不同衬底厚度微带结构紧凑型耦合器的研制
2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524782
D. Letavin
{"title":"Development of Compact Coupler Devices on Microstrip Structures with Different Substrate Thicknesses","authors":"D. Letavin","doi":"10.1109/EWDTS.2018.8524782","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524782","url":null,"abstract":"In this work compact branch-line coupler with the use of microstrip U -shaped containers with different thicknesses of the substrate used are developed. With the help of a specialized program, an assessment was made of how much the change in such a substrate parameter as the thickness of the possibility of miniaturization affects coupler. Miniaturization of the area of devices was realized due to reduction of dimensions with the help of equivalent circuits in the form of a high-resistance line and connected to it in parallel with U-shaped capacitance. The characteristics of this circuit have similar characteristics in the frequency band with the characteristics of the segments used in the standard scheme. Let's consider three variants of designs of power dividers with different substrate thicknesses from 1 to 2 mm, with a step of half a millimeter. Proceeding from this, it was found that when the thickness of the substrate is reduced, the possibilities to reduce the dimensions of the device are increased.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122819473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Compact Digital Orientation Module for Borehole Logging Tools 用于井眼测井工具的紧凑型数字定向模块
2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524792
K. Yusupov, V. Kosarev, A. Mukhametzyanov, Elena Philippova, A. Gavrilov, A. Safiullin, M. Vakhitov, A. Starovoytov, D. Klygach
{"title":"Compact Digital Orientation Module for Borehole Logging Tools","authors":"K. Yusupov, V. Kosarev, A. Mukhametzyanov, Elena Philippova, A. Gavrilov, A. Safiullin, M. Vakhitov, A. Starovoytov, D. Klygach","doi":"10.1109/EWDTS.2018.8524792","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524792","url":null,"abstract":"This paper describes the one-board developed digital orientation system for borehole logging tools, based on FPGA, 3-axis magnetometer and 3-axis accelerometer. The FPGA usage be capable of highspeed measurements orientation parameters (~23 Hz), which necessary for restoring the maneuver in 3-dimensional space of the logging tool with increased depth movement. In addition, the current system can work in conditions of the industrial temperature range. The system test results show the accuracy (up to 1 degree) in determining the azimuth and zenith of the well and logging tool.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126477606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of Digital Gloves with Feedback for VR VR中带反馈的数字手套设计
2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524807
M. Shigapov, V. Kugurakova, Evgeniy Zykov
{"title":"Design of Digital Gloves with Feedback for VR","authors":"M. Shigapov, V. Kugurakova, Evgeniy Zykov","doi":"10.1109/EWDTS.2018.8524807","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524807","url":null,"abstract":"This article describes the first steps in the development of a low-cost digital sensory glove that designed for use in virtual reality systems especially. Existing concepts of gloves differ in features and design, they have various functions, including feedback, tactile feedback to the electric discharge, a feeling of finger bending, finger grip strength and prediction of action and three-dimensional spatial positioning - to improve sensation and practical experience in virtual reality. Manual dynamic perception and freedom of action, common in the real world, provide instant information about objects in the virtual world. Digital gloves act not only as a remote control in VR, but also provide physical feedback for the user when they come in contact with virtual objects. This article presented an own design for inexpensive gloves that allow for proximal and distal finger joint movements, as well as position/orientation determination with an inertial measuring unit. These sensors and tactile feedback caused by the vibration patterns of the coins at the fingertips are integrated into a wireless, easy-to-use and open-source system. The design of hardware, as well as experiment plans for proof of concept, is presented.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125956552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Window-Presum Parametric Discrete Fourier Transform 窗口假定参数离散傅里叶变换
2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524732
O. Ponomareva, A. Ponomarev, N. Ponomareva
{"title":"Window-Presum Parametric Discrete Fourier Transform","authors":"O. Ponomareva, A. Ponomarev, N. Ponomareva","doi":"10.1109/EWDTS.2018.8524732","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524732","url":null,"abstract":"The article gives an analysis of the advantages and disadvantages of the original method for implementing a practical spectrum analyzer based on the discrete Fourier transform (DFT). There are two names used for this method: the weighted overlap-add structure, and the window-presum FFT method. It is shown that the main disadvantage of the weighted superimposition-addition method is the fixation of the central frequencies of the filters of the realized spectrum analyzer. The theoretical foundations of this method have been discovered and investigated. It is shown that the reason for the disadvantage of the method is the procedure used for preliminary data processing in the time domain. Based on the analysis of the DFT matrix, it is shown that the preprocessing procedure used in the time domain is only one of the possible procedures. A generalization of the weighted superposition-addition (FFT method with preliminary summation) is proposed on the basis of a parametric discrete Fourier transform.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"396 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126037503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Using MISR as Countermeasure Against Scan-Based Side-Channel Attacks 利用MISR对抗基于扫描的侧信道攻击
2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524752
Satyadev Ahlawat, Darshit Vaghani, Naveen Bazard, Virendra Singh
{"title":"Using MISR as Countermeasure Against Scan-Based Side-Channel Attacks","authors":"Satyadev Ahlawat, Darshit Vaghani, Naveen Bazard, Virendra Singh","doi":"10.1109/EWDTS.2018.8524752","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524752","url":null,"abstract":"Scan-based Design-for-Test (DfT) feature aims to fulfil the need for better testability and diagnosability of a modern-day VLSI chip. However, an unprotected scan architecture can be exploited by an unauthorized user to steal sensitive data such as a secret encryption key which is embedded on a cryptographic chip. In this work, a new technique is proposed to secure the scan architecture through test authorization mechanism. The proposed technique locks down the scan infrastructure whenever the circuit enters into the test mode of operation. The user needs to pass a test authorization step in order to unlock the scan feature and exercise the scan test. The test authorization step is a one time process which must be passed at the start of the test session. The proposed secure scan test technique has no overhead in terms of test time and test data volume. Furthermore, the proposed secure scan design has marginal area overhead and has similar debug capabilities as the conventional scan design.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128100535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impact of Resistive Open and Bridge Defects on the SET Robustness of Standard CMOS Combinational Logic 阻性开路和电桥缺陷对标准CMOS组合逻辑SET鲁棒性的影响
2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524748
M. Andjelković, Z. Stamenkovic, M. Krstic, R. Kraemer
{"title":"Impact of Resistive Open and Bridge Defects on the SET Robustness of Standard CMOS Combinational Logic","authors":"M. Andjelković, Z. Stamenkovic, M. Krstic, R. Kraemer","doi":"10.1109/EWDTS.2018.8524748","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524748","url":null,"abstract":"The robustness of standard CMOS combinational logic gates to Single Event Transients (SETs), in the presence of resistive open and resistive bridge defects, was investigated. Analysis was performed with SPICE simulations, using the resistors for modeling the open and bridge defects, and a standard double-exponential current source for modeling the SET effects. Two simple circuits based on NAND gate, designed in IHP's 130 nm bulk CMOS process, were employed for this study. It was demonstrated that, for certain input logic levels, the intra- and inter-gate resistive open and bridge defects may lead to significant decrease of the gate's critical charge, and thus to the increase of its soft error rate (SER) by more than one order of magnitude. Also, it was shown that the SET pulse width may significantly increase due to the resistive defects. Simulation results have confirmed that the resistive open defects have a stronger impact on the SET robustness of standard logic gates than the resistive bridge defects.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"81 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128140418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Method for Speeding a Differential Operational Amplifier in the Invert Connection Circuit 在反相连接电路中加速差分运算放大器的方法
2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524711
N. Prokopenko, A. Bugakova, P. Budyakov, A. I. Serebryakov
{"title":"Method for Speeding a Differential Operational Amplifier in the Invert Connection Circuit","authors":"N. Prokopenko, A. Bugakova, P. Budyakov, A. I. Serebryakov","doi":"10.1109/EWDTS.2018.8524711","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524711","url":null,"abstract":"A method for increasing the slew-rate (SRHS) in the invert connection of an operational amplifier (OA) with a dual-input-stage is proposed. The principle of the method includes introduction of two nonlinear differentiating correction circuits (DCc) of the transient into the classical OA circuit which form additional overcharge currents of the integrating capacitance of the OA correction in the high-signal operation. At the same time, the DCcs practically don't affect the small-signal response of the OA. The OA circuits of the proposed subclass can have a low consumption current in the steady-state behavior and be performed on the basis of typical technological processes (CMOS, BiJFet, BJT, SiGe, etc.). The results of computer modeling of BJT OA on integrated transistors of JSC “SPE Pulsar” (Moscow) show that the SRHS of the inverting OA, with ideal current mirrors and the buffer amplifier, increases more than 15 times (to 20,000 V/µs).","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134312191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Application of Monte Carlo Method in the Construction of Copolymerization Process Modeling Algorithm for the Continuous Mode in the Reactors Cascade 蒙特卡罗方法在反应器级联连续模式共聚过程建模算法构建中的应用
2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524789
O. Medvedeva, V. Mikhailov, S. Mustafina, T. Mikhailova, S. Mustafina
{"title":"Application of Monte Carlo Method in the Construction of Copolymerization Process Modeling Algorithm for the Continuous Mode in the Reactors Cascade","authors":"O. Medvedeva, V. Mikhailov, S. Mustafina, T. Mikhailova, S. Mustafina","doi":"10.1109/EWDTS.2018.8524789","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524789","url":null,"abstract":"The article proposes an algorithm for modeling of the process monomers copolymerization, which is carried out in a continuous mode in a cascade of consistently connected reactors of ideal mixing. The algorithm is based on the Monte-Carlo method. It is based on the imitation of growth of each macromolecule of the formed copolymer and fixation of the processes occurring with it. Since the process is conducted in a continuous mode, the algorithm takes into account the distribution of product particles according to the time spent in the system, as well as the constant flow of reaction mixture into the first cascade reactor. The model built on the basis of the algorithm allows to estimate indicators of the product at any time, namely: to predict molecular-mass and viscosity characteristics, mass content of the original monomers in the copolymer, to carry out calculation of molecular-mass distribution, to investigate composite heterogeneity of a product. The proposed algorithm can be implemented as a software tool, in this connection the article proposes an approach to the storage and processing of used data. According to the results of the research a number of computational experiments on modelling of production of butadiene-slipper synthetic rubber in industrial conditions were carried out. The basis of its production is the process of low copolymerization of butadiene with styrene in emulsion. The simulated results reflect consistency with the experimental data.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131802692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design and Test Issues of a SOl CMOS Voltage Controlled Oscillators for Radiation Tolerant Frequency Synthesizers 用于耐辐射频率合成器的SOl CMOS压控振荡器的设计和测试问题
2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524835
D. Sotskov, V. Elesin, G. Nazarova, K. Amburkin, D. Amburkin, G. Chukov, N. Usachev, A. Nikiforov
{"title":"Design and Test Issues of a SOl CMOS Voltage Controlled Oscillators for Radiation Tolerant Frequency Synthesizers","authors":"D. Sotskov, V. Elesin, G. Nazarova, K. Amburkin, D. Amburkin, G. Chukov, N. Usachev, A. Nikiforov","doi":"10.1109/EWDTS.2018.8524835","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524835","url":null,"abstract":"Design and test issues of RF voltage controlled oscillators (VCOs) for space applications are presented. The proposed approach was demonstrated during the design and testing of the differential cross-coupled inductance-capacitance (DCC-LC) VCOs implemented in 350 nm and 180 nm SOI CMOS processes. According to the radiation test results the DCC-LC VCOs are tolerant to total ionizing dose damage up to 300 krad, low-sensitive to heavy ions exposure with LET up to 80 Me V. cm2/mg and can be effectively used in frequency synthesizers for space applications.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"75 13","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114005469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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