Using MISR as Countermeasure Against Scan-Based Side-Channel Attacks

Abstract

Scan-based Design-for-Test (DfT) feature aims to fulfil the need for better testability and diagnosability of a modern-day VLSI chip. However, an unprotected scan architecture can be exploited by an unauthorized user to steal sensitive data such as a secret encryption key which is embedded on a cryptographic chip. In this work, a new technique is proposed to secure the scan architecture through test authorization mechanism. The proposed technique locks down the scan infrastructure whenever the circuit enters into the test mode of operation. The user needs to pass a test authorization step in order to unlock the scan feature and exercise the scan test. The test authorization step is a one time process which must be passed at the start of the test session. The proposed secure scan test technique has no overhead in terms of test time and test data volume. Furthermore, the proposed secure scan design has marginal area overhead and has similar debug capabilities as the conventional scan design.