2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)最新文献_第6页

Enabling exact delay synthesis 实现精确延迟合成

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203799

L. Amarù, Mathias Soeken, P. Vuillod, Jiong Luo, A. Mishchenko, P. Gaillardon, Janet Olson, R. Brayton, G. Micheli

{"title":"Enabling exact delay synthesis","authors":"L. Amarù, Mathias Soeken, P. Vuillod, Jiong Luo, A. Mishchenko, P. Gaillardon, Janet Olson, R. Brayton, G. Micheli","doi":"10.1109/ICCAD.2017.8203799","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203799","url":null,"abstract":"Given (i) a Boolean function, (ii) a set of arrival times at the inputs, and (iii) a gate library with associated delay values, the exact delay synthesis problem asks for a circuit implementation which minimizes the arrival time at the output(s). The exact delay synthesis problem, with given input arrival times, relates to computing the communication complexity of a Boolean function, which is an intractable problem. Input arrival times are variable and can take any value, thereby making the exact delay synthesis search space infinite. This paper presents theory and algorithms for exact delay synthesis. We introduce the theory of equioptimizable arrival times, which allows us to partition all arrival time patterns into a finite set of equivalence classes. Thanks to this new theory, we create for the first time exact delay circuit databases covering all Boolean functions up to 5 variables and all possible arrival time patterns. We describe further arrival time compression techniques which enable the creation of larger databases. We propose an enhanced delay synthesis flow capable of dealing with large circuits, combining exact delay logic rewriting and Boolean optimization techniques, attaining unprecedented results. We improve 9/10 of the best known results in the EPFL arithmetic delay synthesis competition, outperforming previous best results up to 3x. Embedded in a commercial EDA flow for ASICs, our exact delay synthesis techniques reduce the total negative slack by 12.17%, after physical implementation, at negligible area and runtime costs.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115797250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Simultaneous template assignment and layout decomposition using multiple bcp materials in DSA-MP lithography 在DSA-MP光刻中使用多个bcp材料同时分配模板和布局分解

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203784

Kuo-Hao Wu, Shao-Yun Fang

引用次数: 9

Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished 用形式误差保证近似复杂算术电路:完成32位乘法器

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203807

Milan Ceska, Jiří Matyáš, Vojtěch Mrázek, L. Sekanina, Z. Vašíček, Tomáš Vojnar

{"title":"Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplished","authors":"Milan Ceska, Jiří Matyáš, Vojtěch Mrázek, L. Sekanina, Z. Vašíček, Tomáš Vojnar","doi":"10.1109/ICCAD.2017.8203807","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203807","url":null,"abstract":"We present a novel method allowing one to approximate complex arithmetic circuits with formal guarantees on the approximation error. The method integrates in a unique way formal techniques for approximate equivalence checking into a search-based circuit optimisation algorithm. The key idea of our approach is to employ a novel search strategy that drives the search towards promptly verifiable approximate circuits. The method was implemented within the ABC tool and extensively evaluated on functional approximation of multipliers (with up to 32-bit operands) and adders (with up to 128-bit operands). Within a few hours, we constructed a high-quality Pareto set of 32-bit multipliers providing trade-offs between the circuit error and size. This is for the first time when such complex approximate circuits with formal error guarantees have been derived, which demonstrates an outstanding performance and scalability of our approach compared with existing methods that have either been applied to the approximation of multipliers limited to 8-bit operands or statistical testing has been used only. Our approach thus significantly improves capabilities of the existing methods and paves a way towards an automated design process of provably-correct circuit approximations.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126367807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 46

Model and integrate medical resource availability into verifiably correct executable medical guidelines 将医疗资源可用性建模并集成到可验证的正确的可执行医疗指南中

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203885

Chunhui Guo, Zhicheng Fu, Zhenyu Zhang, Shangping Ren, L. Sha

引用次数: 1

Rapid gate sizing with fewer iterations of Lagrangian Relaxation 具有较少拉格朗日松弛迭代的栅极快速定径

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203797

A. Sharma, D. Chinnery, S. Dhamdhere, C. Chu

引用次数: 11

ATRIUM: Runtime attestation resilient under memory attacks ATRIUM:运行时认证在内存攻击下具有弹性

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203803

Shaza Zeitouni, Ghada Dessouky, Orlando Arias, Dean Sullivan, Ahmad Ibrahim, Yier Jin, A. Sadeghi

{"title":"ATRIUM: Runtime attestation resilient under memory attacks","authors":"Shaza Zeitouni, Ghada Dessouky, Orlando Arias, Dean Sullivan, Ahmad Ibrahim, Yier Jin, A. Sadeghi","doi":"10.1109/ICCAD.2017.8203803","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203803","url":null,"abstract":"Remote attestation is an important security service that allows a trusted party (verifier) to verify the integrity of a software running on a remote and potentially compromised device (prover). The security of existing remote attestation schemes relies on the assumption that attacks are software-only and that the prover's code cannot be modified at runtime. However, in practice, these schemes can be bypassed in a stronger and more realistic adversary model that is hereby capable of controlling and modifying code memory to attest benign code but execute malicious code instead — leaving the underlying system vulnerable to Time of Check Time of Use (TOCTOU) attacks. In this work, we first demonstrate TOCTOU attacks on recently proposed attestation schemes by exploiting physical access to prover's memory. Then we present the design and proof-of-concept implementation of ATRIUM, a runtime remote attestation system that securely attests both the code's binary and its execution behavior under memory attacks. ATRIUM provides resilience against both software- and hardware-based TOCTOU attacks, while incurring minimal area and performance overhead.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123855703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 78

Sortex: Efficient timing-driven synthesis of reconfigurable flow-based biochips for scalable single-cell screening Sortex:用于可扩展单细胞筛选的可重构流动生物芯片的高效时序驱动合成

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203835

Mohamed Ibrahim, Aditya Sridhar, K. Chakrabarty, Ulf Schlichtmann

引用次数: 7

Clock-aware placement for large-scale heterogeneous FPGAs 大规模异构fpga的时钟感知布局

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203821

Yun-Chih Kuo, Chau-Chin Huang, Shih-Chun Chen, Chun-Han Chiang, Yao-Wen Chang, S. Kuo

引用次数: 20

Energy efficient runtime approximate computing on data flow graphs 数据流图上的节能运行时近似计算

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203876

Mingze Gao, G. Qu

{"title":"Energy efficient runtime approximate computing on data flow graphs","authors":"Mingze Gao, G. Qu","doi":"10.1109/ICCAD.2017.8203876","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203876","url":null,"abstract":"Approximate computing is an emerging computation paradigm that utilizes many applications' intrinsic error resilience to improve power and energy efficiency. Several approaches have been proposed to identify the non-critical computations by analyzing the output sensitivity to the accuracy of the results, and then perform approximate computing on these computations. However, these static approaches only use the prior knowledge (e.g. input ranges) for analysis and fail to consider the runtime information, which limits the energy saving and incurs large computation error. In this paper, we propose a runtime approximate computing framework to solve this problem. The basic idea is to use a low cost method to estimate the impact of each immediate input value to the accuracy of computation at every node in the data flow graph, and then decide whether we should simply use the estimated value or perform an accurate computation. Our novel runtime estimation method is based on converting data to the logarithmic representation. We propose two algorithms to make the decision at certain nodes whether an accurate computation will be needed to balance energy saving and computation error. Experimental results show that this tradeoff ranges from 40% energy saving with 4.85% error on average to 8% energy saving with 0.18% error. Compared to the static DFG node cutting approach, our approach's estimation accuracy is 32x better to achieve the same amount of energy saving.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123161863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Simple magic: Synthesis and in-memory Mapping of logic execution for memristor-aided logic 简单的魔法:忆阻器辅助逻辑的逻辑执行的综合和内存映射

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203782

Rotem Ben Hur, Nimrod Wald, Nishil Talati, Shahar Kvatinsky

引用次数: 64