2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)最新文献_第5页

An open benchmark implementation for multi-CPU multi-GPU pedestrian detection in automotive systems 汽车系统中多cpu多gpu行人检测的开放基准实现

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203793

Matina Maria Trompouki, Leonidas Kosmidis, N. Navarro

引用次数: 12

Novel heterogeneous computing platforms and 5G communications for IoT applications 面向物联网应用的新型异构计算平台和5G通信

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203872

Yuichi Nakamura, H. Shimonishi, Yuki Kobayashi, K. Satoda, Yashuhiro Matsunaga, Dai Kanetomo

引用次数: 7

Blockage-aware terminal propagation for placement wirelength minimization 阻塞感知终端传播的放置最小的无线长度

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203762

Sheng-Wei Yang, Yao-Wen Chang, Tung-Chieh Chen

{"title":"Blockage-aware terminal propagation for placement wirelength minimization","authors":"Sheng-Wei Yang, Yao-Wen Chang, Tung-Chieh Chen","doi":"10.1109/ICCAD.2017.8203762","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203762","url":null,"abstract":"Wirelength is the most fundamental objective in placement because it also affects various placement metrics (routability, timing, etc.). Half-perimeter wirelength (HPWL) is a pervasive metric for circuit placement. However, preplaced blocks (i.e., blockages) might misguide an HPWL-based placer to generate a placement solution that incurs significant routing detours. Consequently, it is desirable to develop an effective method to resolve the HPWL-rooted routing detour problem for placement optimization. This paper presents an efficient, generic, yet effective terminal propagation algorithm as a pre-placement process which can readily be integrated into a traditional placement flow to improve wirelength (and routability). Our algorithm identifies a region for each preplaced terminal according to its connectivity, and applies a minimum-cost maximum flow algorithm to propagate all preplaced terminals to their feasible propagation locations with the minimum total propagation length. Experimental results show that our flow with terminal propagation can reduce both global routed wirelength and routing congestion by 4% on average, compared with one without terminal propagation. In particular, our work also provides a long unnoticed insight into placement optimization with blockages, which can be addressed with an efficient, generic, yet effective scheme.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131010549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Transportation security in the era of autonomous vehicles: Challenges and practice 自动驾驶汽车时代的交通安全:挑战与实践

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203895

S. Ray

引用次数: 2

A novel cache bank timing attack 一种新的缓存库定时攻击方法

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203771

Z. Jiang, Yunsi Fei

{"title":"A novel cache bank timing attack","authors":"Z. Jiang, Yunsi Fei","doi":"10.1109/ICCAD.2017.8203771","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203771","url":null,"abstract":"To avoid information leakage through execution, modern software implementations of cryptographic algorithms target constant timing complexity, i.e., the number of instructions does not vary with different inputs. However, often times, the underlying microarchitecture behaves differently under different data inputs, which covertly leaks confidential information through the timing channel. Cache timing channel due to cache miss penalties has been explored in recent years to break system security. In this paper, we exploit a finer-grained L1 cache bank timing channel, the stalling delay due to cache bank conflicts, and develop a new timing attack against table lookup-based cryptographic algorithms. We implement the timing attack with three different methods on Sandy Bridge micro-architecture, and successfully recover the complete 128-bit AES encryption key. The most effective attack can achieve 50% success rate using 75,000 samples and 100% success rate using 200,000 samples. The whole attack process from collecting samples to recoverying all key bytes takes less than 3 minutes. We anticipate the new timing attack to be a threat to various platforms, including ARM-based smart phones and performance-critical accelerators like GPUs.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122142995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

ICCAD-2017 CAD contest in multi-deck standard cell legalization and benchmarks ICCAD-2017 CAD大赛中多层标准单元的合法化和基准

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203870

Nima Karimpour Darav, Ismail Bustany, A. Kennings, Ravi Mamidi

引用次数: 31

Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations 可重用性是FIRRTL的基础:硬件构造语言、编译器框架和转换

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203780

Adam M. Izraelevitz, Jack Koenig, Patrick Li, Richard Lin, Angie Wang, Albert Magyar, Donggyu Kim, Colin Schmidt, Chick Markley, Jim Lawson, J. Bachrach

{"title":"Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations","authors":"Adam M. Izraelevitz, Jack Koenig, Patrick Li, Richard Lin, Angie Wang, Albert Magyar, Donggyu Kim, Colin Schmidt, Chick Markley, Jim Lawson, J. Bachrach","doi":"10.1109/ICCAD.2017.8203780","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203780","url":null,"abstract":"Enabled by modern languages and retargetable compilers, software development is in a virtual “Cambrian explosion” driven by a critical mass of powerfully parameterized libraries; but hardware development practices lag far behind. We hypothesize that existing hardware construction languages (HCLs) and novel hardware compiler frameworks (HCFs) can put hardware development on a similar evolutionary path by enabling new hardware libraries to be independent of underlying process technologies including FPGA mappings. We support this claim by (1) evaluating the degree with which Chisel, an existing HCL, can support powerfully parameterized libraries, and (2) introducing the concept and implementation of an HCF that uses an open-source hardware intermediate representation, FIRRTL (Flexible Intermediate Representation for RTL), to transform target-independent RTL into technology-specific RTL. Finally, we evaluate many hardware compiler transformations, including simplifying transformations, analyses, optimizations, instrumentations, and specializations, which demonstrate the power of a combined HCL and HCF approach.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115399448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 130

Towards reliability-aware circuit design in nanoscale FinFET technology: — New-generation aging model and circuit reliability simulator 面向纳米级FinFET技术的可靠性感知电路设计——新一代老化模型和电路可靠性模拟器

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203856

Shaofeng Guo, Runsheng Wang, Zhuoqing Yu, P. Hao, P. Ren, Yangyuan Wang, S. Liao, Chunyi Huang, Tianlei Guo, A. Chen, Jushan Xie, Ru Huang

{"title":"Towards reliability-aware circuit design in nanoscale FinFET technology: — New-generation aging model and circuit reliability simulator","authors":"Shaofeng Guo, Runsheng Wang, Zhuoqing Yu, P. Hao, P. Ren, Yangyuan Wang, S. Liao, Chunyi Huang, Tianlei Guo, A. Chen, Jushan Xie, Ru Huang","doi":"10.1109/ICCAD.2017.8203856","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203856","url":null,"abstract":"In this paper, an industry-level new-generation EDA solution for reliability-aware design in nanoscale FinFET technology is presented for the first time, with new compact transistor aging models and upgraded circuit reliability simulator. Our work solves various issues found in FinFET silicon data of NBTI aging. Especially, instead of ignoring or less accurate NBTI recovery effect model in traditional simulators, accurate NBTI degradation and recovery models are proposed and validated by silicon data for full stress/recovery range in the FinFET technology. The history effect, one of the important features of NBTI which is missing in the existing industrial tools, is included based on new simulation methodology. Since FinFET reliability data suggests the conventional linear extrapolation method is no longer valid, an accurate fast-speed long-term prediction method is proposed based on smart iteration flows of equivalence. The frequency dependence of NBTI, which draws much attention, is included in the new simulator automatically. This work has been integrated into Cadence reliability simulator, providing designers an opportunity for accurate reliability-aware circuit design.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123256810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

An assessment of vulnerability of hardware neural networks to dynamic voltage and temperature variations 硬件神经网络对动态电压和温度变化的脆弱性评估

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203882

Xun Jiao, Mulong Luo, Jeng-Hau Lin, Rajesh K. Gupta

{"title":"An assessment of vulnerability of hardware neural networks to dynamic voltage and temperature variations","authors":"Xun Jiao, Mulong Luo, Jeng-Hau Lin, Rajesh K. Gupta","doi":"10.1109/ICCAD.2017.8203882","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203882","url":null,"abstract":"As a problem solving method, neural networks have shown broad applicability from medical applications, speech recognition, and natural language processing. This success has even led to implementation of neural network algorithms into hardware. In this paper, we explore two questions: (a) to what extent microelectronic variations affects the quality of results by neural networks; and (b) if the answer to first question represents an opportunity to optimize the implementation of neural network algorithms. Regarding first question, variations are now increasingly common in aggressive process nodes and typically manifest as an increased frequency of timing errors. Combating variations — due to process and/or operating conditions — usually results in increased guardbands in circuit and architectural design, thus reducing the gains from process technology advances. Given the inherent resilience of neural networks due to adaptation of their learning parameters, one would expect the quality of results produced by neural networks to be relatively insensitive to the rising timing error rates caused by increased variations. On the contrary, using two frequently used neural networks (MLP and CNN), our results show that variations can significantly affect the inference accuracy. This paper outlines our assessment methodology and use of a cross-layer evaluation approach that extracts hardware-level errors from twenty different operating conditions and then inject such errors back to the software layer in an attempt to answer the second question posed above.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128851469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 34

Cost-effective write disturbance mitigation techniques for advancing PCM density 提高PCM密度的低成本写入干扰缓解技术

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203786

Mohammad Khavari Tavana, D. Kaeli

{"title":"Cost-effective write disturbance mitigation techniques for advancing PCM density","authors":"Mohammad Khavari Tavana, D. Kaeli","doi":"10.1109/ICCAD.2017.8203786","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203786","url":null,"abstract":"Rapid technology scaling has enabled the integration of many cores into a single chip. Given this level of core integration, the requirements for a large and scalable main memory system will only grow. Current DRAM-based main memory systems face power and scalability issues when working at sub-micron scales. Phase Change Memory (PCM) has been proposed as one of the most promising technology candidates to replace or complement DRAM. However, scaling down cell sizes introduces significant thermal-based write disturbance challenges in PCM. Due to the heat generated for programming cells, neighboring cells may be disturbed, experiencing changes in their values. A naive solution is to increase inter-cell space, attempting to isolate cell programming and eliminating write disturbance, but this approach significantly reduces PCM density. In this paper, we propose two cost-effective solutions to reduce the probability of write disturbance. Our solutions come with few side-effects on other memory system metrics. The first technique is based on data encoding, and tries to reduce the number of vulnerable data patterns when writing data to main memory. The second technique detects vulnerable cells, and overwrites them if their occurrence is below a set threshold. The proposed techniques are general and can avoid much of the performance overhead introduced by write disturbance. Our proposed solutions can reduce the average number of writes by 49% over traditional schemes, while incurring minimal impact on PCM lifetime and energy consumption.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116209722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7