Towards reliability-aware circuit design in nanoscale FinFET technology: — New-generation aging model and circuit reliability simulator

In this paper, an industry-level new-generation EDA solution for reliability-aware design in nanoscale FinFET technology is presented for the first time, with new compact transistor aging models and upgraded circuit reliability simulator. Our work solves various issues found in FinFET silicon data of NBTI aging. Especially, instead of ignoring or less accurate NBTI recovery effect model in traditional simulators, accurate NBTI degradation and recovery models are proposed and validated by silicon data for full stress/recovery range in the FinFET technology. The history effect, one of the important features of NBTI which is missing in the existing industrial tools, is included based on new simulation methodology. Since FinFET reliability data suggests the conventional linear extrapolation method is no longer valid, an accurate fast-speed long-term prediction method is proposed based on smart iteration flows of equivalence. The frequency dependence of NBTI, which draws much attention, is included in the new simulator automatically. This work has been integrated into Cadence reliability simulator, providing designers an opportunity for accurate reliability-aware circuit design.