2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)最新文献_第3页

Adaptive error recovery in MEDA biochips based on droplet-aliquot operations and predictive analysis 基于微滴等分操作和预测分析的MEDA生物芯片自适应误差恢复

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203834

Zhanwei Zhong, Zipeng Li, K. Chakrabarty

引用次数: 23

Memristor-based perceptron classifier: Increasing complexity and coping with imperfect hardware 基于忆阻器的感知器分类器:增加复杂性和应对不完善的硬件

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203825

F. Merrikh-Bayat, M. Prezioso, B. Chakrabarti, I. Kataeva, D. Strukov

{"title":"Memristor-based perceptron classifier: Increasing complexity and coping with imperfect hardware","authors":"F. Merrikh-Bayat, M. Prezioso, B. Chakrabarti, I. Kataeva, D. Strukov","doi":"10.1109/ICCAD.2017.8203825","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203825","url":null,"abstract":"We experimentally demonstrate classification of 4×4 binary images into 4 classes, using a 3-layer mixed-signal neuromorphic network (“MLP perceptron”), based on two passive 20×20 memristive crossbar arrays, board-integrated with discrete CMOS components. The network features 10 hidden-layer and 4 output-layer analog CMOS neurons and 428 metal-oxide memristors, i.e. is almost an order of magnitude more complex than any previously reported functional passive (0T1R) memristor classifier. Moreover, the inference operation of this classifier is performed entirely in the integrated hardware. To deal with larger crossbar arrays, we have developed a semiautomatic approach to their forming and testing, and compared several memristor training schemes for coping with imperfect behavior of these devices, as well as with variability of analog CMOS neurons. The effectiveness of the proposed schemes for defect and variation tolerance was verified experimentally using the implemented network and, additionally, by modeling the operation of a larger network, with 300 hidden-layer neurons, on the MNIST benchmark. Finally, we propose a simple modification of the implemented memristor-based vector-by-matrix multiplier to allow its operation in a wider temperature range.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114864545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

Mixed-cell-height detailed placement considering complex minimum-implant-area constraints 考虑复杂最小植入面积约束的混合细胞高度详细放置

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203761

Yen-Yi Wu, Yao-Wen Chang

{"title":"Mixed-cell-height detailed placement considering complex minimum-implant-area constraints","authors":"Yen-Yi Wu, Yao-Wen Chang","doi":"10.1109/ICCAD.2017.8203761","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203761","url":null,"abstract":"Mixed-cell-height circuits have prevailed in advanced technology to address various design needs. Along with device scaling, complex minimum-implant-area (MIA) constraints arise as an emerging challenge in modern circuit designs, adding to the difficulties in mixed-cell-height placement. Existing MIA-aware detailed placement with single-row-height standard cells is insufficient for mixed-cell-height designs: (1) filler insertion, typically used to resolve MIA violations, might incur unaffordable area and wirelength overheads, and (2) mixed-height cell perturbation could cause severe inter-row MIA violations. This paper presents the first work to address the mixed-cell-height detailed placement problem considering both intra- and inter-row MIA constraints. We first fix intra-row violations by clustering violating mixed-height cells of the same threshold voltage, and then perturb each cluster to obtain a desired cell permutation by applying an efficient, optimal dynamic-programming-based algorithm for a special case and Algorithm DLX for general ones, where a provably constant performance ratio for a mixed-cell-height reshaping problem can be achieved. With a network-flow-based formulation, remaining violating cells are placed in appropriate filler-insertion positions to fix cell violations and minimize area. After performing mixed-cell-height detailed placement, we finally fix inter-row violations by shifting violating cells in minimum displacement. Compared with a filler insertion method and a greedy clustering approach, experimental results show that our proposed algorithm can resolve all MIA violations with smallest HPWL and area overheads in reasonable running time.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121906542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

NEMESIS: A software approach for computing in presence of soft errors NEMESIS:一种在存在软错误时进行计算的软件方法

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203792

Moslem Didehban, Aviral Shrivastava, Sai Ram Dheeraj Lokam

引用次数: 23

A spike-based long short-term memory on a neurosynaptic processor 在神经突触处理器上的基于尖峰的长短期记忆

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203836

Amar Shrestha, Khadeer Ahmed, Yanzhi Wang, D. Widemann, A. Moody, B. V. Essen, Qinru Qiu

{"title":"A spike-based long short-term memory on a neurosynaptic processor","authors":"Amar Shrestha, Khadeer Ahmed, Yanzhi Wang, D. Widemann, A. Moody, B. V. Essen, Qinru Qiu","doi":"10.1109/ICCAD.2017.8203836","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203836","url":null,"abstract":"Low-power brain-inspired hardware systems have gained significant traction in recent years. They offer high energy efficiency and massive parallelism due to the distributed and asynchronous nature of neural computation through low-energy spikes. One such platform is the IBM TrueNorth Neurosynaptic System. Recently TrueNorth compatible representation learning algorithms have emerged, achieving close to state-of-the-art performance in various datasets. An exception is its application in temporal sequence processing models such as recurrent neural networks (RNNs), which is still at the proof of concept level. This is partly due to the hardware constraints in connectivity and syn-aptic weight resolution, and the inherent difficulty in capturing temporal dynamics of an RNN using spiking neurons. This work presents a design flow that overcomes the aforementioned difficulties and maps a special case of recurrent networks called Long Short-Term Memory (LSTM) onto a spike-based platform. The framework is built on top of various approximation techniques, weight and activation discretization, spiking neuron sub-circuits that implements the complex gating mechanisms and a store-and-release technique to enable neuron synchronization and faithful storage. While many of the techniques can be applied to map LSTM to any SNN simulator/emulator, here we demonstrate this approach on the TrueNorth chip adhering to its constraints. Two benchmark LSTM applications, parity check and Extended Reber Grammar, are evaluated and their accuracy, energy and speed tradeoffs are analyzed.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115943220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Exploring cache bypassing and partitioning for multi-tasking on GPUs 探索gpu上的多任务缓存绕过和分区

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203754

Yun Liang, Xiuhong Li, Xiaolong Xie

{"title":"Exploring cache bypassing and partitioning for multi-tasking on GPUs","authors":"Yun Liang, Xiuhong Li, Xiaolong Xie","doi":"10.1109/ICCAD.2017.8203754","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203754","url":null,"abstract":"Graphics Processing Units (GPUs) computing has become ubiquitous for embedded system, evidenced by its wide adoption for various general purpose applications. As more and more applications are accelerated by GPUs, multi-tasking scenario starts to emerge. Multi-tasking allows multiple applications to simultaneously execute on the same GPU and share the resource. This brings new challenges due to the contention among the different applications for the shared resources such as caches. However, the caches on GPUs are difficult to use. If used inappropriately, it may hurt the performance instead of improving it. In this paper, we propose to use cache partitioning together with cache bypassing as the shared cache management mechanism for multi-tasking on GPUs. The combined approach aims to reduce the interference among the tasks and preserve the locality for each task. However, the interplay among the cache partitioning and bypassing brings greater challenges. On one hand, the partitioned cache space to each task affects its cache bypassing decision. On the other hand, cache bypassing affects the cache capacity required for each task. To address this, we propose a two-step approach. First, we use cache partitioning to assign dedicated cache space to each task to reduce the interference among the tasks. During this process, we compare cache partitioning with coarse-grained cache bypassing. Then, we use fine-grained cache bypassing to selectively bypass certain data requests and threads for each task. We explore different cache partitioning and bypassing designs and demonstrate the potential benefits of this approach. Experiments using a wide range of applications demonstrate that our technique improves the overall system throughput by 52% on average compared to the default multi-tasking solution on GPUs.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"230 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126684519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Scalable N-worst algorithms for dynamic timing and activity analysis 动态定时和活动分析的可扩展n -最差算法

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203830

Hari Cherupalli, J. Sartori

{"title":"Scalable N-worst algorithms for dynamic timing and activity analysis","authors":"Hari Cherupalli, J. Sartori","doi":"10.1109/ICCAD.2017.8203830","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203830","url":null,"abstract":"As the overheads for ensuring the correctness of electronic designs continue to increase with continued technology scaling and increased variability, better-than-worst-case (BTWC) design has gained significant attention. Many BTWC design techniques utilize dynamic timing and activity information for design analysis and optimization. These techniques rely on path-based analysis that enumerates the exercised paths in a design as targets for analysis and optimization. However, path-based dynamic analysis techniques are not scalable and cannot be used to analyze full processors and full applications. On the other hand, graph-based techniques like those that form the foundational building blocks of electronic design automation tools are scalable and can efficiently analyze large designs. In this paper, we extend graph-based analysis to provide the fundamental dynamic analysis tools necessary for BTWC design, analysis, and optimization. Specifically, we present scalable graph-based techniques to report the N-worst exercised paths in a design for three metrics — timing criticality (slack), activity (toggle count), and activity subject to delay constraints. Compared to existing path-based techniques, our scalable dynamic analysis techniques improve average performance by 977 x, 163 x, and 113 x, respectively, and enable scalable analysis for a full processor design running full applications.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127402322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Functional safety methodologies for automotive applications 汽车应用的功能安全方法

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203886

A. Nardi, A. Armato

引用次数: 44

GRASP based metaheuristics for layout pattern classification 基于GRASP的布局模式分类元启发式方法

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203820

M. Woo, Seungwon Kim, Seokhyeong Kang

引用次数: 9

DtCraft: A distributed execution engine for compute-intensive applications DtCraft:用于计算密集型应用程序的分布式执行引擎

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203853

Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong

引用次数: 8