2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)最新文献_第2页

VST: A virtual stress testing framework for discovering bugs in SSD flash-translation layers VST:用于发现SSD闪存转换层中的错误的虚拟压力测试框架

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203790

Ren-Shuo Liu, Yun-Sheng Chang, Chih-Wen Hung

{"title":"VST: A virtual stress testing framework for discovering bugs in SSD flash-translation layers","authors":"Ren-Shuo Liu, Yun-Sheng Chang, Chih-Wen Hung","doi":"10.1109/ICCAD.2017.8203790","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203790","url":null,"abstract":"Flash translation layers (FTLs) are the core embedded software (also known as firmware) of NAND flash-based solid-state drives (SSDs). The relentless pursuit of high-performance SSDs renders FTLs increasingly complex and intricate. Therefore, testing and validating FTLs are crucial and challenging tasks. Directly testing and validating FTLs on SSD hardware are common practices though, they are time-consuming and cumbersome because 1) the testing speed is limited by the hardware speed of SSDs and 2) just reproducing bugs can be challenging, let alone locating and root causing the bugs. This work presents virtual stress testing (VST), a simulation framework to enable executing SSD FTLs on PCs or servers against virtual SRAM, DRAM, and flash emulated by host-side main memory. FTL function calls, such as moving data from flash to DRAM, are served by the VST framework. Therefore, VST can test FTLs without SSD hardware requirements nor SSD speed limitations, and root causing bugs becomes manageable tasks. We apply VST to representative SSD design, OpenSSD, which is actively utilized and maintained by SSD and FTL communities. Experimental results show that VST can test FTLs at a speed up to 375 GB/s, which is several hundred times faster than directly testing FTLs on SSD hardware. Moreover, we successfully discover seven new FTL bugs in the OpenSSD design using VST, which is a solid evidence of VST's bug-discovering effectiveness.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124820909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Data path optimisation and delay matching for asynchronous bundled-data balsa circuits 异步捆绑数据接口电路的数据路径优化和延迟匹配

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203806

Norman Kluge, Ralf Wollowski

引用次数: 0

Machine learning on FPGAs to face the IoT revolution fpga上的机器学习面对物联网革命

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203862

Xiaofan Zhang, Anand Ramachandran, Chuanhao Zhuge, Di He, Wei Zuo, Zuofu Cheng, K. Rupnow, Deming Chen

引用次数: 57

An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs 一种基于集成展开式的大规模混合电路设计宏细化算法

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203818

Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen

{"title":"An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs","authors":"Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen","doi":"10.1109/ICCAD.2017.8203818","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203818","url":null,"abstract":"With the increasing use of pre-designed macros in a modern chip and its induced high design complexity, macro placement has become a challenging problem in today's design houses. Most popular macro placement algorithms adopt a three-stage approach: placement prototyping, macro placement, and standard-cell placement, where cell positions after macro placement are assumed the same as those at the prototyping stage, possibly misguiding succeeding standard-cell placement. To close the gap between macro and standard-cell placement, we propose a macro-refining algorithm that adopts an integrated spreading technique considering the spreading of both macros and cells and the dynamic information of cell positions to improve macro placement. We further propose a new force-modulation technique to refine macro placement and a congestion-aware macro shifter to preserve more space for better routability. Extensive experiments based on various macro placements show that our proposed techniques are effective and our macro-refining algorithm can find significantly better placement solutions for large-scale mixed-size circuit designs.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130244738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Impact of circuit-level non-idealities on vision-based autonomous driving systems 电路级非理想性对基于视觉的自动驾驶系统的影响

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203887

Handi Yu, Changhao Yan, Xuan Zeng, Xin Li

引用次数: 3

A streaming clustering approach using a heterogeneous system for big data analysis 使用异构系统进行大数据分析的流聚类方法

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203845

Dajung Lee, Alric Althoff, D. Richmond, R. Kastner

{"title":"A streaming clustering approach using a heterogeneous system for big data analysis","authors":"Dajung Lee, Alric Althoff, D. Richmond, R. Kastner","doi":"10.1109/ICCAD.2017.8203845","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203845","url":null,"abstract":"Data clustering is a fundamental challenge in data analytics. It is the main task in exploratory data mining and a core technique in machine learning. As the volume, variety, velocity, and variability of data grows, we need more efficient data analysis methods that can scale towards increasingly large and high dimensional data sets. We develop a streaming clustering algorithm that is highly amenable to hardware acceleration. Our algorithm eliminates the need to store the data objects, which removes limits on the size of the data that we can analyze. Our algorithm is highly parameterizable, which allows it to fit to the characteristics of the data set, and scale towards the available hardware resources. Our streaming hardware core can handle more than 40 Msamples/s when processing 3-dimensional streaming data and up to 1.78 Msamples/s for 70-dimensional data. To validate the accuracy and performance of our algorithms we compare it with several common clustering techniques on several different applications. The experimental result shows that it outperforms other prior hardware accelerated clustering systems.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"519 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123120711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

SALT: Provably good routing topology by a novel steiner shallow-light tree algorithm SALT:用一种新的steiner浅光树算法证明了良好的路由拓扑结构

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203828

Gengjie Chen, Peishan Tu, Evangeline F. Y. Young

引用次数: 23

Making split fabrication synergistically secure and manufacturable 使分体制造协同安全性和可制造性

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203794

Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, J. Rajendran

引用次数: 5

Switch cell optimization of power-gated modern system-on-chips 电源门控现代片上系统的开关单元优化

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.1109/ICCAD.2017.8203826

Dongyoun Yi, Taewhan Kim

{"title":"Switch cell optimization of power-gated modern system-on-chips","authors":"Dongyoun Yi, Taewhan Kim","doi":"10.1109/ICCAD.2017.8203826","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203826","url":null,"abstract":"This work addresses a practical problem of allocating and placing a minimal number of active switch cells in power gated modern System-on-Chips (SoCs) to save the unnecessary standby leakage under noise (i.e., IR-drop) constraint. Since power gating switch cells are physically directly connected to power rails, their overall allocation structure is synthesized in a stage before the logic cell placement. Consequently, the allocation of switch cells in the pre-placement could lead to unnecessarily high standby leakage for modern designs. This work proposes a practical remedy for this problem at the post-placement stage. Specifically, for an initial design with a grid-based switch cell allocation, which is commonly used design methodology in industry, we propose a comprehensive solution to determining, for each switch cell, (1) whether the cell can be permanently turned off or (2) the type of switch cell for replacement so that the resulting total standby leakage of switch cells should be minimized under the noise constraint. We formulate the problem into a variant of weighted set cover problem and solve it efficiently by employing an approximate set cover algorithm. Through experiments with benchmark circuits in ISCAS89, OPENMSP430, and FPU, it is shown that our method is able to reduce the standby leakage by 35.0% and 13.9% over the initial designs and the designs produced by the previous switch cell optimization method in [5], respectively.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131239244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications COMBA:一个全面的基于模型的分析框架，用于实际应用程序的高级综合

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2017-11-13 DOI: 10.5555/3199700.3199757

Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He

{"title":"COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications","authors":"Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He","doi":"10.5555/3199700.3199757","DOIUrl":"https://doi.org/10.5555/3199700.3199757","url":null,"abstract":"High Level Synthesis (HLS) relies on the use of synthesis pragmas to generate digital designs meeting a set of specifications. However, the selection of a set of pragmas depends largely on designer experience and knowledge of the target architecture and digital design. Existing automated methods of pragma selection are very limited in scope and capability to analyze complex design descriptions in high-level languages to be synthesized using HLS. In this paper, we propose COMBA, a comprehensive model-based analysis framework capable of analyzing the effects of a multitude of pragmas related to functions, loops and arrays in the design description using pluggable analytical models, a recursive data collector (RDC) and a metric-guided design space exploration algorithm (MGDSE). When compared with HLS tools like Vivado HLS, COMBA reports an average error of around 1% in estimating performance, while taking only a few seconds for analysis of Polybench benchmark applications and a few minutes for real-life applications like JPEG, Seidel and Rician. The synthesis pragmas recommended by COMBA result in an average 100x speed-up in performance for the analyzed applications, which establishes COMBA as a superior alternative to current state-of-the-art approaches.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116531548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 85