Data path optimisation and delay matching for asynchronous bundled-data balsa circuits

Abstract

Balsa provides an open-source design flow where asynchronous circuits are created from high-level specifications, but the syntax-driven translation often results in performance overhead. To improve this, we exploit the fact that bundled-data circuits can be divided into data and control path. Hence, tailored optimisation techniques can be applied to both paths separately. For control path optimisation, STG-based resynthesis has been used (applying logic minimisation). To continue the investigation, we additionally apply synchronous standard tools to optimise the data path. However, this removes the matched delays needed for a properly working bundled-data circuit. Therefore, we also present two algorithms to automatically insert proper matched delays. Our experiments show a performance improvement of up to 44 % and energy consumption improvement of up to 60 % compared to the original Balsa implementation.