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Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)最新文献

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Smart power: From problem statement to system solution 巧实力:从问题陈述到系统解决
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603142
D. Draxelmayr, K. Norling, C. Lindholm
{"title":"Smart power: From problem statement to system solution","authors":"D. Draxelmayr, K. Norling, C. Lindholm","doi":"10.1109/PRIME.2013.6603142","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603142","url":null,"abstract":"This paper demonstrates the design of a high power, high efficiency inverter based on SiC (Silicon Carbide) JFET (Junction Field Effect Transistor) switches. It starts with a problem statement, i.e. which requirements are to be fulfilled, discusses design solutions, and ends with some measurements of the complete system. The final design is able to handle more than 1000V, currents of more than 30A and achieves a peak efficiency of more than 99% in a buck configuration [1].","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130016340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 36μW rail-to-rail-input chopper stabilized amplifier using correlated double sampling 采用相关双采样的36μW轨对轨输入斩波稳定放大器
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603126
A. Pipino, M. De Blasi, M. De Matteis, S. D’Amico, A. Fornasari, A. Baschirotto
{"title":"A 36μW rail-to-rail-input chopper stabilized amplifier using correlated double sampling","authors":"A. Pipino, M. De Blasi, M. De Matteis, S. D’Amico, A. Fornasari, A. Baschirotto","doi":"10.1109/PRIME.2013.6603126","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603126","url":null,"abstract":"This paper describes a chopper stabilized amplifier, obtained using an input chopper for modulation, an AC coupling for offset rejection and a correlated double sampling structure for demodulation, avoiding ripple spurs. The operational amplifier has a rail-to-rail input stage, with a supply voltage range from 1.8V to 5V. It is characterized by a multipath nested Miller compensation network with double pole-zero cancellation. The circuit achieves a simulated 130dB-dc-gain with a current consumption of 20μA, suitable for low-power application. Equivalent input offset has been evaluated by Montecarlo simulations demonstrating a maximum standard deviation of about 4μV.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130018337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Simulated power analysis attacks on a DDPL crypto-core without routing constraints 在没有路由约束的DDPL加密核上模拟功率分析攻击
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603185
Simone Bongiovanni, G. Scotti, A. Trifiletti
{"title":"Simulated power analysis attacks on a DDPL crypto-core without routing constraints","authors":"Simone Bongiovanni, G. Scotti, A. Trifiletti","doi":"10.1109/PRIME.2013.6603185","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603185","url":null,"abstract":"Delay-based Dual-rail Pre-charge Logic (DDPL) is a logic style introduced with the aim of hiding power consumption in cryptographic circuits in order to prevent Power Analysis (PA) attacks. Its particular data encoding allows to make the adsorbed current constant for each data input combination, irrespective of capacitive load conditions, which allows to design a PA-resistant circuit without routing constraints. In this work we present a fair comparison between SABL, a well-known state of the art transistor level countermeasure which is sensitive to the capacitive mismatches on the complementary lines and requires a customized routing procedure, and DDPL. After having provided a power model for describing the leakage sources for the above mentioned logics, a simple cryptographic circuit has been designed for both SABL and DDPL, and a CPA attack has been mounted. Simulations results show that when capacitive load unbalances are considered, DDPL strongly outperforms SABL in terms of number of traces required for disclose the secret key.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"57 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116313528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CIRSIUM: A circuit simulator in MATLAB® with object oriented design CIRSIUM: MATLAB®中的电路模拟器，具有面向对象的设计
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603134
A. G. Mahmutoglu, A. Demir
{"title":"CIRSIUM: A circuit simulator in MATLAB® with object oriented design","authors":"A. G. Mahmutoglu, A. Demir","doi":"10.1109/PRIME.2013.6603134","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603134","url":null,"abstract":"We present CIRSIUM, a CIRcuit SImulator Using MATLAB® and its object oriented programming language. CIRSIUM has been developed as a flexible and modular framework in order to enable the rapid development of new device models and prototyping of new circuit analysis paradigms and algorithms. The modular core code includes the PSP MOSFET compact model and uses SUNDIALS for the solution of dynamical circuit equations. New device models can be added by supplying their stamps in vector/matrix form, and existing models can be translated from the Verilog-A hardware description language using ADMS that automatically computes the necessary Jacobians. CIRSIUM has been initially developed for the analysis of random telegraph signal (RTS) noise in nano-scale integrated circuits. For this purpose, the PSP MOSFET compact model has been expanded with a detailed, non-stationary RTS noise model, that includes a physical description of gate oxide defects and the calculation of their voltage and position dependent capture/emission time constants. Future applications of CIRSIUM will include non-electronic systems, such as noise modeling and analysis for biological neurons, neuronal networks and the nervous system.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121955661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Scalable hybrid CORDIC-LUT architectures for CG-FFT processors 用于CG-FFT处理器的可扩展混合CORDIC-LUT架构
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603119
A. Congiu, A. Picciau, M. Barbaro, E. Bodano
{"title":"Scalable hybrid CORDIC-LUT architectures for CG-FFT processors","authors":"A. Congiu, A. Picciau, M. Barbaro, E. Bodano","doi":"10.1109/PRIME.2013.6603119","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603119","url":null,"abstract":"In this work we introduce Processing Element (PE) scalability in twiddle factor generators for FFT processors. First the twiddle factor indexing scheme for Constant Geometry FFT is analyzed and a CORDIC-based novel algorithm is deduced. It uses single-step rotations and does not need any CORDIC gain correction. Then, two architectures implementing the algorithm are presented with the goal of scalability. The first (shared core) is characterized by both low register count and variable throughput, while the second (pipelined) achieves the maximum throughput during the whole computation. Our hybrid models use both one ROM and multiplier-based CORDIC modules. The designs are then evaluated in terms of register usage and output error, showing scalability of register bits as a function of the number of PEs if compared to other architectures. Architectures were coded in VHDL and synthesized on a Xilinx Virtex-5 330T FPGA.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130257313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Analog performance of PD-SOI MOSFETs at high temperatures using reverse body bias 使用反向体偏置的PD-SOI mosfet在高温下的模拟性能
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603144
A. Schmidt, H. Kappert, R. Kokozinski
{"title":"Analog performance of PD-SOI MOSFETs at high temperatures using reverse body bias","authors":"A. Schmidt, H. Kappert, R. Kokozinski","doi":"10.1109/PRIME.2013.6603144","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603144","url":null,"abstract":"The analog performance, i.e. intrinsic gain and bandwidth, of SOI (Silicon-on-Insulator) MOSFETs in a wide temperature range up to 400°C has so far been strongly affected by device leakage currents. Thereby the moderate inversion region as a preferred point of operation has been unusable as leakage currents dominate drain currents at high temperatures. In this paper we present a reverse body biasing (RBB) approach to improve the transistor's analog performance up to 400°C. Thereby operation in the lower moderate inversion region of the SOI transistor device is feasible. The method allows beneficial FD (fully depleted) device characteristics in a 1.0 μm PD (partially depleted) SOI CMOS process. NHGATE and PHGATE devices with an H-shaped gate have been investigated. Results report a significant improvement of the gm/Id factor and the intrinsic gain Ai in the moderate inversion region by applying RBB.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127704435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Random interleaved pipeline countermeasure against power analysis attacks 随机交错管道对抗功率分析攻击
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603113
R. Menicocci, A. Trifiletti, F. Trotta
{"title":"Random interleaved pipeline countermeasure against power analysis attacks","authors":"R. Menicocci, A. Trifiletti, F. Trotta","doi":"10.1109/PRIME.2013.6603113","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603113","url":null,"abstract":"An RTL countermeasure intended to protect the AddRoundKey and SubByte steps of the AES algorithm against DPA or CPA attacks has been proposed and tested on an AES encoding coprocessor implemented on FPGA. Experimental results based on first order CPA attacks confirmed the effectiveness of the proposed countermeasure, especially in protecting the SBOX output, showing that even with the acquisition of 300000 power curves, the absolute value of correlation function is embedded in the measured noise floor and there are no peaks able to reveal the encryption key.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115895819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design-space exploration of an eFPGA soft-core based on Multi-Stages Switching Networks 基于多级交换网络的eFPGA软核的设计空间探索
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603104
Matteo Cuppini, E. F. Scarselli, C. Mucci
{"title":"Design-space exploration of an eFPGA soft-core based on Multi-Stages Switching Networks","authors":"Matteo Cuppini, E. F. Scarselli, C. Mucci","doi":"10.1109/PRIME.2013.6603104","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603104","url":null,"abstract":"Embedded FPGAs are becoming appealing IPs to enhance modern SoCs, since technology scaling is enabling reconfigurability at lower area impact. This notwithstanding, to become effective eFPGAs should be highly adaptable to support application-specific optimization, in terms of DSP blocks, technology options and floorplan requirements. For that, in this paper, we analyse a soft-core eFPGA template based on Multi-Stage Switching Network which couples high flexibility with a modular design approach based on the regular replication of few simple switch modules for the programmable routing. Implementation on 65nm technology showed the existence of a significantly wide design space which allows to quickly optimize the device for area, speed and/or leakage power. Results show that depending on architectural and technology options adopted, performance can vary in terms of area (~50%), speed (+/-30%) and leakage (~90%) with respect to a reference design.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126826139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Analysis and modeling of minority carrier injection in deep-trench based BCD technologies 基于BCD技术的深沟少量载流子注入分析与建模
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603160
Michael Kollmitzer, M. Olbrich, E. Barke
{"title":"Analysis and modeling of minority carrier injection in deep-trench based BCD technologies","authors":"Michael Kollmitzer, M. Olbrich, E. Barke","doi":"10.1109/PRIME.2013.6603160","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603160","url":null,"abstract":"This paper proposes a methodology for circuit simulation of parasitic effects caused by minority carrier injection into the substrate of a deep-trench based BCD technology. An equivalent circuit is used containing pre-calculated macro models for the injecting diode, the substrate of the chip and the sensitive diode. The macro models are generated by means of TCAD simulations which determine the carrier density distribution in the substrate. The carrier density in the substrate at the sensitive pn-junction is directly related to the parasitic current of the device. The results of the simulations are verified by test chip measurements.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122893366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A MEMS-based oscillator with synchronous amplitude control 基于mems的同步幅度控制振荡器
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603129
J. Gronicz, N. Chekurov, L. Aaltonen, K. Halonen
{"title":"A MEMS-based oscillator with synchronous amplitude control","authors":"J. Gronicz, N. Chekurov, L. Aaltonen, K. Halonen","doi":"10.1109/PRIME.2013.6603129","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603129","url":null,"abstract":"This paper describes the design and simulation of a MEMS-based oscillator with a silicon tuning fork as frequency selective element. The interface electronics include a synchronous amplitude control circuit that allows for precise control of oscillation amplitude. The nominal oscillation frequency is 1.8 MHz. The structure has been implemented using a 0.35 μm High Voltage CMOS process and operates with a nominal supply of 3.3V.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"29 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113975962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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