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Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)最新文献

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An inductorless 34 Gbit/s half-rate 4:1 multiplexer in 0.25-μm SiGe technology 无电感34 Gbit/s半速率4:1多路复用器，采用0.25-μm SiGe技术
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603165
M. Khafaji, C. Carta, E. Sobotta, D. Micusík, F. Ellinger
{"title":"An inductorless 34 Gbit/s half-rate 4:1 multiplexer in 0.25-μm SiGe technology","authors":"M. Khafaji, C. Carta, E. Sobotta, D. Micusík, F. Ellinger","doi":"10.1109/PRIME.2013.6603165","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603165","url":null,"abstract":"This paper demonstrates a 34 Gbit/s 4:1 multiplexer with 200 mW power dissipation in a 0.25-μm SiGe process. A multiphase clock architecture at half-rate clock is chosen to reduce the power dissipation. In addition, stability issues caused by the capacitively loaded clock driver are studied and a solution is proposed with a suitable compensation circuit. Measurement results are presented as well. The output signals yield open eye diagrams at the highest available test rate of 34 Gbit/s, while presenting rise and fall times below 12 ps.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"827 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114557483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Innovative RFDAC concepts for digital multi-mode transmitter in cellular applications 创新RFDAC概念，用于蜂窝应用中的数字多模发射机
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603139
M. Fulde, F. Kuttner, E. Thaller, D. Ponton, V. Kampus, S. Gruenberger, H. Habibovic, A. Santner, C. Duller, C. Krassnitzer, G. Babin, G. Knoblinger
{"title":"Innovative RFDAC concepts for digital multi-mode transmitter in cellular applications","authors":"M. Fulde, F. Kuttner, E. Thaller, D. Ponton, V. Kampus, S. Gruenberger, H. Habibovic, A. Santner, C. Duller, C. Krassnitzer, G. Babin, G. Knoblinger","doi":"10.1109/PRIME.2013.6603139","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603139","url":null,"abstract":"Digital polar transmitter concepts based on RF-DA-converter recently proved the potential to significantly reduce power consumption. Furthermore, external component count as well as PCB area is minimized since no TX SAW filter is required and a single multimode, multiband power amplifier can be used.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129350882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of PA class on reconstruction filters sizing for a WCDMA base station LINC transmitter PA等级对WCDMA基站LINC发射机重构滤波器尺寸的影响
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603118
N. Prou, F. Riviere, C. Berland
{"title":"Impact of PA class on reconstruction filters sizing for a WCDMA base station LINC transmitter","authors":"N. Prou, F. Riviere, C. Berland","doi":"10.1109/PRIME.2013.6603118","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603118","url":null,"abstract":"The LInear amplification with Nonlinear Component transmitter is a high power efficient architecture for radio communication systems. Nevertheless, this architecture is sensitive to mismatches between the two paths and its efficiency performances are dependent on the power amplification stage topology. Additively, careful attention has to be paid to baseband performances in terms of sampling rate, Digital to Analog Converters (DACs) resolution, reconstruction filter bandwidth. In this paper, we present the specification of the reconstruction filters for a single carrier WCDMA 3GPP base station transmitter and this, according to the Power Amplifier (PA) class (switched mode (SMPA) or AB class). We address the impact of the class of the PAs on the overall performances and on the reconstruction filters specifications. Admissible time delays and gain mismatches between the two paths will also be quantified.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126387896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Bluetooth transceiver modeling using SystemC-AMS 使用SystemC-AMS进行蓝牙收发器建模
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603099
Fangyan Li, Remi Butaud, E. Dekneuvel, G. Jacquemod
{"title":"Bluetooth transceiver modeling using SystemC-AMS","authors":"Fangyan Li, Remi Butaud, E. Dekneuvel, G. Jacquemod","doi":"10.1109/PRIME.2013.6603099","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603099","url":null,"abstract":"This paper presents the high-level modeling and simulation of a GFSK RF transceiver for a Bluetooth Low Energy (BLE) system. This model, written in SystemC-AMS (SCAMS) permits a simple integration within the existing system digital environment written in SystemC-TLM, which enables a global system simulation to obtain the system performance (e.g. Bit-Error-Rate (BER) or Packet- Error-Rate (PER)) related to the power and energy consumption.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130075880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A new decoding solution for the asynchronous sigma delta modulator 一种新的异步σ δ调制器译码方案
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603115
Wei Chen, C. Papavassiliou
{"title":"A new decoding solution for the asynchronous sigma delta modulator","authors":"Wei Chen, C. Papavassiliou","doi":"10.1109/PRIME.2013.6603115","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603115","url":null,"abstract":"A new type of low power decoding circuit for asynchronous sigma delta modulators is presented. The circuit implements a special coarse-fine time-to-digital converter to quantize the square wave produced by asynchronous sigma delta modulators, and converts the duty cycle to a digital output. The time-to-digital converter operates asynchronously by utilizing vernier delay lines. The purpose of this circuit is to achieve a high resolution with a low frequency sampling clock, which is suitable for the ultra-low power applications. The proposed circuit is designed in 0.35um. Spectre simulations, show an 11-bit resolution is realized with 0.06LSB integral non-linearity and 0.04LSB differential non-linearity. The simulated power consumption is below16uW from a dual 0.6 V supply voltage.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122679196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A MEMS BPSK demodulator: Micromechanical Mixing and Filtering using MetalMUMPs MEMS BPSK解调器:金属mumps的微机械混合和滤波
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603128
J. Scerri, I. Grech, E. Gatt, O. Casha
{"title":"A MEMS BPSK demodulator: Micromechanical Mixing and Filtering using MetalMUMPs","authors":"J. Scerri, I. Grech, E. Gatt, O. Casha","doi":"10.1109/PRIME.2013.6603128","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603128","url":null,"abstract":"In this paper two MEMS structures that are intended to demodulate a BPSK low data rate signal are compared. They are designed in conformity with the MetalMUMPs process. Target applications for such devices would be low-rate, wireless personal area networks (LR-WPANs) such as those described in the IEEE 802.15.4 standard onto which the ZigBee standard is built. The presented MEMS structures mix the Radio Frequency (RF) and Local Oscillator (LO) signals electrostatically and also filter this mixed signal prior to electrostatic sensing. These MEMS structures can also be used as the building blocks to demodulate higher order PSK schemes. The first structures' mode of vibration is torsional in nature and the use of torsional vibrations for BPSK demodulation is innovative. The first structure has an undamped resonant frequency of 2 MHz. The second structure is an extension of the first and is also supported on tethers exhibiting torsional vibrations. This structure resonates at 680 kHz.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131452844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Application of Bayesian networks to predict SMART power semiconductor lifetime 贝叶斯网络在SMART功率半导体寿命预测中的应用
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603175
K. Plankensteiner, Olivia Bluder, J. Pilz
{"title":"Application of Bayesian networks to predict SMART power semiconductor lifetime","authors":"K. Plankensteiner, Olivia Bluder, J. Pilz","doi":"10.1109/PRIME.2013.6603175","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603175","url":null,"abstract":"In this paper Bayesian networks are used to model semiconductor lifetime data from a cyclic stress test system. The data of interest is a mixture of log-normal distributions, representing different failure mechanisms and moreover, the data is censored. To understand the complex lifetime behavior, interactions between test settings, geometric designs, material properties and physical parameters of the semiconductor device are modeled by a Bayesian network. For the network's structure and parameter learning statistical toolboxes in MATLAB have been extended and applied. Due to censored observations MCMC simulations are necessary to determine the posterior distribution. For model selection the ARD algorithm and goodness of fit criteria such as marginal likelihoods, Bayes factors, posterior predictive density distributions and SSEPs are used. The results indicate that the application of Bayesian networks to semiconductor reliability provides useful information about the interactions between covariates and serves as a reliable alternative to currently applied methods.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124704545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Direct Digital Frequency Synthesizers implemented on high end FPGA devices 直接数字频率合成器在高端FPGA器件上实现
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603105
M. Genovese, E. Napoli
{"title":"Direct Digital Frequency Synthesizers implemented on high end FPGA devices","authors":"M. Genovese, E. Napoli","doi":"10.1109/PRIME.2013.6603105","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603105","url":null,"abstract":"Direct Digital Frequency Synthesizer (DDFS) circuits are routinely implemented in many electronic systems. Advanced DDFS design techniques have been proposed and optimized for ASIC (Application Specific Integrated Circuits) implementations. Nowadays, FPGA devices are frequently chosen as target for digital circuits. This paper presents the FPGA implementation of state of the art DDFS architectures and compares their performance providing hints on optimal design as a function of the chosen performance parameter.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130668758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An ultra-thin CMOS in-plane stress sensor 超薄CMOS平面内应力传感器
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603172
Y. Mahsereci, N. Wacker, H. Richter, J. Burghartz
{"title":"An ultra-thin CMOS in-plane stress sensor","authors":"Y. Mahsereci, N. Wacker, H. Richter, J. Burghartz","doi":"10.1109/PRIME.2013.6603172","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603172","url":null,"abstract":"This paper presents a CMOS stress sensor for uniaxial, in-plane flex measurement. The sensor is to be fabricated as an ultra-thin chip in order to adapt to surface shape. The sensor generates 2×10-bit data from piezo-resistive elements, via on chip stress insensitive readout circuitry. Unlike the directional selectivity of the strain gauges, the uniaxial in-plane stress vector can be measured in any direction by this sensor. In addition, the MOSFET stress macro model used for the sensor flex simulations is presented. It is used for the sensor flex simulations. It supports DC, AC, and transient analysis with any analog simulator.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134120582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Variable-step 12-bit ADC based on counter ramp recycling architecture suitable for CMOS imagers with column-parallel readout 基于计数器斜坡循环架构的可变步进12位ADC，适用于具有列并行读出的CMOS成像仪
Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) Pub Date : 2013-06-24 DOI: 10.1109/PRIME.2013.6603107
T.M. Hassan, M. Strobel, H. Richter, J. Burghartz
{"title":"Variable-step 12-bit ADC based on counter ramp recycling architecture suitable for CMOS imagers with column-parallel readout","authors":"T.M. Hassan, M. Strobel, H. Richter, J. Burghartz","doi":"10.1109/PRIME.2013.6603107","DOIUrl":"https://doi.org/10.1109/PRIME.2013.6603107","url":null,"abstract":"A 12-bit counter ramp recycling analog-to-digital converter (ADC) is proposed, which can be configured in a single-step mode for achieving high conversion accuracy as well as in various multi-step modes for yielding high conversion speed. A unique ADC circuit realization is used for the different modes of operation, while a digital control unit is responsible for providing the necessary control signals to the ADC. Similar to common counter ramp architectures, the proposed implementation is suitable for column-parallel readout owing to its simplicity. The proposed variable-step recycling ADC is implemented in a 0.18μm CMOS technology from UMC. Simulation results show good agreement with the expected trade-off between speed and accuracy, which is common to all conventional ADCs.","PeriodicalId":125553,"journal":{"name":"Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"298 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133435086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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