2016 IEEE 34th VLSI Test Symposium (VTS)最新文献

WeSPer: A flexible small delay defect quality metric WeSPer:一个灵活的小延迟缺陷质量度量

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477266

Omar Al-Terkawi Hasib, Y. Savaria, C. Thibeault

{"title":"WeSPer: A flexible small delay defect quality metric","authors":"Omar Al-Terkawi Hasib, Y. Savaria, C. Thibeault","doi":"10.1109/VTS.2016.7477266","DOIUrl":"https://doi.org/10.1109/VTS.2016.7477266","url":null,"abstract":"Testing for small delay defects (SDDs) is important due to their dominance in recent technology nodes. Unfortunately, all the SDD test quality metrics in the literature limit their assessment to the size of the delay defect tested under at-speed or slower clocks, which makes their results misleading under special cases such as faster-than-at-speed testing. Moreover, those metrics are inadequate for assessing the quality of recent SDD test methods that consider the variation of delays in a circuit. In this paper, a novel flexible SDD quality metric that can be adapted according to the available information and the applied test method is proposed. The proposed metric is named Weighted Slack Percentage (WeSPer) as it is defined by a slack ratio weighted by confidence level (CL) multipliers. The flexibility comes from the ability to model test inaccuracies or delay varying effects into the CL multipliers. This paper presents the WeSPer metric, along with a CL multiplier that penalizes overtesting to give a more accurate assessment of the quality of faster-than-at-speed testing. The metric is calculated for several benchmark circuits and compared to other SDD metrics found in the literature. The results show that WeSPer is better than other metrics at representing the quality of SDD tests, especially under faster-than-at-speed testing.","PeriodicalId":124707,"journal":{"name":"2016 IEEE 34th VLSI Test Symposium (VTS)","volume":"272 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114105629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Test implications and challenges in near threshold computing special session 近阈值计算特殊会话的测试意义和挑战

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477295

M. Tahoori, R. Aitken, S. Vangal, Bal Sandhu

引用次数: 1

Security primitives (PUF and TRNG) with STT-MRAM 具有STT-MRAM的安全原语(PUF和TRNG)

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477292

E. Vatajelu, G. D. Natale, P. Prinetto

引用次数: 11

Process independent gain measurement with low overhead via BIST/DUT co-design 通过BIST/DUT协同设计实现低开销的过程独立增益测量

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477284

J. Jeong, J. Kitchen, S. Ozev

{"title":"Process independent gain measurement with low overhead via BIST/DUT co-design","authors":"J. Jeong, J. Kitchen, S. Ozev","doi":"10.1109/VTS.2016.7477284","DOIUrl":"https://doi.org/10.1109/VTS.2016.7477284","url":null,"abstract":"Built-in Self-Test (BIST) is essential, particularly for radio frequency (RF) devices where off-chip RF signal analysis is costly or in some cases, infeasible. Two major problems have made RF BIST elusive. First, process variations make the BIST circuit behavior hard to predict, limiting accuracy of measurements. Second, the overhead, particularly in terms of performance degradation, make RF BIST undesirable. In this paper, we address these two issues for RF BIST gain measurement. First, we show that by setting up relative gain measurements and carefully crafting the BIST methodology and the matching BIST circuit, the effect of process variations on measurement accuracy can be suppressed. Second, by co-designing the BIST circuit together with the device under test (DUT), performance impact can be eliminated or significantly reduced. To demonstrate the proposed approach, we design a low noise amplifier (LNA) as the DUT together with the BIST circuit. We also design a stand-alone LNA with the same specifications and manufacture these two circuits on the same die. We show that the LNA gain can be determined very accurately, using only DC measurements, and the performance impact of the BIST circuit is negligible.","PeriodicalId":124707,"journal":{"name":"2016 IEEE 34th VLSI Test Symposium (VTS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127390923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Effective generation and evaluation of diagnostic SBST programs 诊断性SBST程序的有效生成和评估

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477279

Andreas Riefert, R. Cantoro, M. Sauer, M. Reorda, B. Becker

{"title":"Effective generation and evaluation of diagnostic SBST programs","authors":"Andreas Riefert, R. Cantoro, M. Sauer, M. Reorda, B. Becker","doi":"10.1109/VTS.2016.7477279","DOIUrl":"https://doi.org/10.1109/VTS.2016.7477279","url":null,"abstract":"Functional test and software-based self-test (SBST) approaches for processors are becoming popular as they enable low-cost production tests and are often the only solution for in-field tests. With the increasing use of volume diagnosis, efficient and cost-effective diagnosis methods are required. A high quality functional or SBST test program can be used to perform logic fault diagnosis with low-cost test equipment and therefore significantly reduce the cost of diagnosis. We present a framework for the automatic generation of functional diagnostic sequences for stuck-at faults. The framework allows a user to specify constraints imposed by the employed test environment and generates diagnostic sequences satisfying these constraints. Furthermore, the framework is able to prove the equivalence of faults under the specified constraints. This enables to compute the best possible diagnostic quality that can be reached under the given environmental constraints. Also, it gives the necessary information for implementing selective DFT techniques in order to differentiate faults which cannot be distinguished otherwise. In our experiments we evaluated a MIPS-like processor. The results show that our approach can effectively distinguish fault pairs or prove their equivalence, under different environmental constraints. To the best, of our knowledge, this is the first approach which, enables the automatic generation of diagnostic SBST, programs and allows to eectively prove the equivalence of faults in functional and SBST test environments.","PeriodicalId":124707,"journal":{"name":"2016 IEEE 34th VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126952031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results 使用老化现场监测器的早期系统故障预测:实施方法和应用结果

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477316

L. Anghel, A. Benhassain, A. Sivadasan, F. Cacho, V. Huard

引用次数: 4

Dynamic docking architecture for concurrent testing and peak power reduction 动态对接架构，用于并发测试和峰值功耗降低

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477290

Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, A. Sanghani, Karthikeyan Natarajan, J. E. Colburn, Anubhav Sinha

引用次数: 2

Consistency in wafer based outlier screening 基于晶圆的异常值筛选的一致性

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477267

Sebastian Siatkowski, Chuanhe Jay Shan, Li-C. Wang, N. Sumikawa, W. R. Daasch, J. Carulli

引用次数: 6

Process variation oriented delay testing of SRAMs 基于工艺变化的sram延迟测试

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477286

X. Zuo, S. Gupta

引用次数: 0

Performance enhancement techniques and verification methods for radio frequency circuits and systems 射频电路和系统的性能增强技术和验证方法

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477276

Hari Chauhan, M. Onabajo

引用次数: 3