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2016 IEEE 34th VLSI Test Symposium (VTS)最新文献

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A programmable method for low-power scan shift in SoC integrated circuits SoC集成电路中低功耗扫描移位的可编程方法
2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477289
Ran Wang, Bonita Bhaskaran, Karthikeyan Natarajan, Ayub Abdollahian, Kaushik Narayanun, K. Chakrabarty, A. Sanghani
{"title":"A programmable method for low-power scan shift in SoC integrated circuits","authors":"Ran Wang, Bonita Bhaskaran, Karthikeyan Natarajan, Ayub Abdollahian, Kaushik Narayanun, K. Chakrabarty, A. Sanghani","doi":"10.1109/VTS.2016.7477289","DOIUrl":"https://doi.org/10.1109/VTS.2016.7477289","url":null,"abstract":"We present a programmable method for shift-clock stagger assignment to reduce power supply noise during system-on-chip (SoC) testing. An SoC design is typically composed of several blocks and two neighboring blocks that share the same power rails should not be toggled at the same time during shift. Therefore, the proposed programmable method does not assign the same stagger value to neighboring blocks. The positions of all blocks are first analyzed and the shared boundary length between blocks is then calculated. Based on the position relationships between the blocks, a mathematical model is presented to derive optimal result for small-to-medium sized problems. For larger designs, a heuristic algorithm is proposed and evaluated. We present assignment results as well as power-analysis results and silicon data for industry designs to highlight the effectiveness of the proposed method.","PeriodicalId":124707,"journal":{"name":"2016 IEEE 34th VLSI Test Symposium (VTS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122084786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Runtime resource management for lifetime extension in multi-core systems 多核系统中生命周期扩展的运行时资源管理
2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477317
Cristiana Boichini
{"title":"Runtime resource management for lifetime extension in multi-core systems","authors":"Cristiana Boichini","doi":"10.1109/VTS.2016.7477317","DOIUrl":"https://doi.org/10.1109/VTS.2016.7477317","url":null,"abstract":"The availability of numerous, possibly heterogeneous, processing resources in multi-core systems allows one to exploit them to optimize performance and/or power/energy consumption. In particular, strategies have been defined to map and schedule tasks on the system resources, with the aim of optimizing the adopted figure of merit, at design time, if the working context is known in advance and relatively stable, at run time when facing changing/unpredictable working conditions. However, it is important to be aware that such strategies may have an impact on the overall lifetime of the system because of aging and wear-out mechanisms. Therefore such management strategies, generally adopted for handling performance and power consumption aspects, should be enhanced in order to consider such issues. Furthermore, specific Dynamic Reliability Management (DRM) policies have been devised to deal with lifetime issues in multi-core systems, acting mainly on the workload distribution (and eventually on architectural knobs, such as voltage/frequency scaling) to mitigate the stress caused by the running applications. Here we will focus on DRM strategies, whose goal is pursuing the improvement of lifetime reliability by means of load distribution policies that identify the resource where to map a new application entering the system, or where to periodically migrate tasks to balance stress. More precisely, a selection of state-of-the-art solutions will be presented and analysed, with respect to the achieved expected lifetime, evaluated when considering the first failure as well as the sequence of failures leading to the system being unable to fulfill the user's performance of service requirements.","PeriodicalId":124707,"journal":{"name":"2016 IEEE 34th VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122164829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Online soft-error vulnerability estimation for memory arrays 存储阵列在线软错误漏洞估计
2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477301
Arunkumar Vijayan, Abhishek Koneru, Mojtaba Ebrahimi, K. Chakrabarty, M. Tahoori
{"title":"Online soft-error vulnerability estimation for memory arrays","authors":"Arunkumar Vijayan, Abhishek Koneru, Mojtaba Ebrahimi, K. Chakrabarty, M. Tahoori","doi":"10.1109/VTS.2016.7477301","DOIUrl":"https://doi.org/10.1109/VTS.2016.7477301","url":null,"abstract":"Radiation-induced soft errors are a major reliability concern in circuits fabricated at advanced technology nodes. Online soft-error vulnerability estimation offers the flexibility of exploiting dynamic fault-tolerant mechanisms for cost-effective reliability enhancement. We propose a generic run-time method with low area and power overhead to predict the soft-error vulnerability of on-chip memory arrays. The vulnerability prediction is based on signal probabilities (SPs) of a small set of flip-flops, chosen at design time, by studying the correlation between the soft-error vulnerability and the flip-flop SPs for representative workloads. We exploit machine learning to develop a predictive model that can be deployed in the system in software form. Simulation results on two processor designs show that the proposed technique can accurately estimate the soft-error vulnerability of on-chip memory arrays that constitute the instruction cache, the data cache, and the register file.","PeriodicalId":124707,"journal":{"name":"2016 IEEE 34th VLSI Test Symposium (VTS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123180345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A convergent procedure for partially-reachable states 部分可达状态的收敛过程
2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477264
I. Pomeranz
{"title":"A convergent procedure for partially-reachable states","authors":"I. Pomeranz","doi":"10.1109/VTS.2016.7477264","DOIUrl":"https://doi.org/10.1109/VTS.2016.7477264","url":null,"abstract":"Partially-functional broadside tests attempt to maintain close-to-functional operation conditions by using scan-in states that are referred to as partially-reachable. An earlier procedure starts from the fully-unspecified state, and uses fully-specified primary input vectors to compute partially-specified states that are partially-reachable. The procedure is divergent in that the number of states it considers increases with every iteration. This paper describes a new, convergent procedure that starts from a subset of reachable states, and uses the fully-unspecified primary input vector to compute partially-reachable states. The procedure typically converges without any additional constraints. By starting from reachable states, the convergent procedure captures functional constraints that cannot be obtained by the divergent procedure starting from the fully-unspecified state. Experimental results for benchmark circuits demonstrate the implications on the generation of partially-functional broadside tests.","PeriodicalId":124707,"journal":{"name":"2016 IEEE 34th VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125779624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of crosstalk and process variation on capture power reduction for at-speed test 串扰和工艺变化对高速试验捕获功率降低的影响
2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477291
Surya Piplani, G. Visweswaran, Anshul Kumar
{"title":"Impact of crosstalk and process variation on capture power reduction for at-speed test","authors":"Surya Piplani, G. Visweswaran, Anshul Kumar","doi":"10.1109/VTS.2016.7477291","DOIUrl":"https://doi.org/10.1109/VTS.2016.7477291","url":null,"abstract":"In this paper we discuss the need to consider Crosstalk and Process Variation effects for test power reduction during Launch-on-Capture scheme for at-speed delay test. We show that consideration of these effects can have significant effect on capture power reduction technique. This effect is a manifestation of increased IR drops in the presence of crosstalk and process variation. Thus both these factors should be taken into account during the design as well as the test phase of nanometer technologies. Our experimental results on two significantly sized industrial designs in 28nm show that when these effects are considered the number of high capture power patterns selected for post-processing are impacted by 13% and 30% respectively. Thus not considering these effects might lead to some high power consuming patterns left untouched or over processing of the patterns.","PeriodicalId":124707,"journal":{"name":"2016 IEEE 34th VLSI Test Symposium (VTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127031426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On-die learning-based self-calibration of analog/RF ICs 基于片内学习的模拟/射频集成电路自校准
2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477297
G. Volanis, Dzmitry Maliuk, Yichuan Lu, K. S. Subramani, A. Antonopoulos, Y. Makris
{"title":"On-die learning-based self-calibration of analog/RF ICs","authors":"G. Volanis, Dzmitry Maliuk, Yichuan Lu, K. S. Subramani, A. Antonopoulos, Y. Makris","doi":"10.1109/VTS.2016.7477297","DOIUrl":"https://doi.org/10.1109/VTS.2016.7477297","url":null,"abstract":"We discuss a methodology and the corresponding hardware architecture for performing self-calibration of analog/RF ICs through the use of on-die learning. More specifically, we introduce the design of an on-chip analog neural network which can be trained to implement a non-linear regression function. This regression function is, then, used to approximate a Figure-of-Merit (FoM) reflecting the performances of an analog/RF IC. As an input to this regression function, we use the readings of low-cost on-chip sensors in response to simple on-chip generated stimuli. The FoM is predicted for all possible settings of the knobs provided for calibrating the chip performances and the best option is retained. The proposed methodology is demonstrated on a tunable Low-Noise Amplifier (LNA) which was designed and fabricated in IBM's 130nm RF CMOS process. Experimental results show that the proposed self-calibration method achieves not only significant yield enhancement but also a compelling optimization of the LNA's overall performance across the entire chip population.","PeriodicalId":124707,"journal":{"name":"2016 IEEE 34th VLSI Test Symposium (VTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115016621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Special panel session IIB: "System validation and silicon debug — Is standardization possible?" 专题小组会议IIB:“系统验证和芯片调试——标准化是否可行?”
2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-01 DOI: 10.1109/VTS.2016.7477311
M. Ricchetti, Eric Rentschler, Amitava Majumdar, Mike Lowe, M. LaVine, S. Lindsey, Sharad Kumar
{"title":"Special panel session IIB: \"System validation and silicon debug — Is standardization possible?\"","authors":"M. Ricchetti, Eric Rentschler, Amitava Majumdar, Mike Lowe, M. LaVine, S. Lindsey, Sharad Kumar","doi":"10.1109/VTS.2016.7477311","DOIUrl":"https://doi.org/10.1109/VTS.2016.7477311","url":null,"abstract":"Although there are standards for DFT, there are none for Design for Debug and Validation (DFD/DFV) of silicon in systems. Many semiconductor companies have standardized DFD/DFV architectures and features within their own products, however these are proprietary solutions. The panel will explore whether or not these solutions share common requirements and will debate whether the industry would benefit from any standardization, and what to standardize. Examples are standard debug infrastructure IP, bridges to software debug and support for EDA automation.","PeriodicalId":124707,"journal":{"name":"2016 IEEE 34th VLSI Test Symposium (VTS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125954807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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