2016 IEEE 34th VLSI Test Symposium (VTS)最新文献_第2页

Test method and scheme for low-power validation in modern SOC integrated circuits 现代SOC集成电路低功耗验证的测试方法和方案

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477310

Bonita Bhaskaran, A. Sanghani, Kaushik Narayanun, Ayub Abdollahian, A. Laknaur

引用次数: 5

Cache- and register-aware system reliability evaluation based on data lifetime analysis 基于数据生命周期分析的缓存和寄存器感知系统可靠性评估

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477299

Maha Kooli, Firas Kaddachi, G. D. Natale, A. Bosio

{"title":"Cache- and register-aware system reliability evaluation based on data lifetime analysis","authors":"Maha Kooli, Firas Kaddachi, G. D. Natale, A. Bosio","doi":"10.1109/VTS.2016.7477299","DOIUrl":"https://doi.org/10.1109/VTS.2016.7477299","url":null,"abstract":"Developing new methods to evaluate the software reliability in an early design stage of the system can save the design costs and efforts, and will positively impact product time-to-market. This paper introduces a new approach to evaluate, at early design phase, the reliability of a computing system running a software. The approach can be used when the hardware architecture is not completely defined yet. In order to be independent of the hardware architecture and at the same time accurate, we propose to use the Low-Level Virtual Machine (LLVM) framework. In addition, to reduce the reliability evaluation time, our approach consists in analyzing the variable lifetimes to compute the probability of masked faults. Finally, to achieve a better characterization we propose to consider also the presence of caches and register files. For this purpose, a cache emulator as well as a register file emulator are developed. Simulations run with our approach produce very similar results to those run with a hardware-based fault injector. This proves the accuracy of our approach to evaluate system reliability with a gain in the simulation time and without requiring a hardware platform.","PeriodicalId":124707,"journal":{"name":"2016 IEEE 34th VLSI Test Symposium (VTS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130729966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Predicting Vt mean and variance from parallel Id measurement with model-fitting technique 用模型拟合技术预测平行Id测量的均值和方差

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477268

Chih-Ying Tsai, Kao-Chi Lee, Chien-Hsueh Lin, Sung-Chu Yu, Wen-Rong Liau, A. Hou, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, M. Chao

引用次数: 3

Fault modeling and testing of resistive nonvolatile-8T SRAMs 电阻性非易失性8t ram的故障建模与测试

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477303

Yu-Ting Li, Yong-Xiao Chen, Jin-Fu Li

引用次数: 3

Post fabrication tuning of GaN based RF power amplifiers for pico-cell applications 微电池应用中基于GaN的射频功率放大器的加工后调谐

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477275

M. R. Hasin, J. Kitchen

引用次数: 0

Path constraint solving based test generation for observability-enhanced branch coverage 基于路径约束求解的可观察性增强分支覆盖测试生成

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477265

Yanhong Zhou, Huawei Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li

引用次数: 0

Adaptive testing of analog/RF circuits using hardware extracted FSM models 自适应测试模拟/射频电路使用硬件提取FSM模型

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477283

Sabyasachi Deyati, B. Muldrey, A. Chatterjee

{"title":"Adaptive testing of analog/RF circuits using hardware extracted FSM models","authors":"Sabyasachi Deyati, B. Muldrey, A. Chatterjee","doi":"10.1109/VTS.2016.7477283","DOIUrl":"https://doi.org/10.1109/VTS.2016.7477283","url":null,"abstract":"The test generation problem for analog/RF circuits has been largely intractable due to the fact that repetitive circuit simulation for test stimulus optimization is extremely time-consuming. As a consequence, it is difficult, if not impossible, to generate tests for practical mixed-signal/RF circuits that include the effects of tester inaccuracies and measurement noise. To offset this problem and allow test generation to scale to different applications, we propose a new approach in which FSM models of mixed-signal/RF circuits are abstracted from hardware measurements on fabricated devices. These models allow accurate simulation of device behavior under arbitrary stimulus and thereby test stimulus generation, even after the device has been shipped to a customer. As a consequence, it becomes possible to detect process shifts with fine granularity and regenerate tests to adapt to process perturbations in a dynamic manner without losing test accuracy. A complete methodology for such adaptive testing of mixed-signal/RF circuits is developed in this paper. Simulation results and hardware measurements are used to demonstrate the efficacy of the proposed techniques.","PeriodicalId":124707,"journal":{"name":"2016 IEEE 34th VLSI Test Symposium (VTS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126322895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Infant mortality tests for analog and mixed-signal circuits 模拟和混合信号电路的婴儿死亡率测试

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477262

Suvadeep Banerjee, S. Natarajan

引用次数: 3

Security of emerging non-volatile memories: Attacks and defenses 新兴非易失性记忆的安全性:攻击与防御

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477293

Kaveh Shamsi, Yier Jin

引用次数: 19

Yield improvement of an EEPROM for automotive applications while maintaining high reliability 在保持高可靠性的同时，提高了汽车用EEPROM的产量

2016 IEEE 34th VLSI Test Symposium (VTS) Pub Date : 2016-04-25 DOI: 10.1109/VTS.2016.7477269

G. Schatzberger, F. Leisenberger, Peter Sarson

引用次数: 1