2015 IEEE International Integrated Reliability Workshop (IIRW)最新文献_第3页

The strength of BEOL structures fabricated using low K materials and its impact on CPI failures 低K材料制备的BEOL结构强度及其对CPI失效的影响

2015 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2015-10-01 DOI: 10.1109/IIRW.2015.7437081

T. Shaw, X. Liu, E. Misra, D. Questad, G. Bonilla, T. Wassick, M. Lamorey, H. Shobha, G. Osborne, D. Kioussis, J. Wright, R. Bisson, I. Paquin, S. Bouchard, S. Tetreault, D. Stone, C. Muzzy, B. Sundlof, T. Daubenspeck

{"title":"The strength of BEOL structures fabricated using low K materials and its impact on CPI failures","authors":"T. Shaw, X. Liu, E. Misra, D. Questad, G. Bonilla, T. Wassick, M. Lamorey, H. Shobha, G. Osborne, D. Kioussis, J. Wright, R. Bisson, I. Paquin, S. Bouchard, S. Tetreault, D. Stone, C. Muzzy, B. Sundlof, T. Daubenspeck","doi":"10.1109/IIRW.2015.7437081","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437081","url":null,"abstract":"The paper examines the factors that affect the formation of delaminations under C4 joints during chip joining. Through multiscale finite element modeling and chip joining experiments we find that two important parameters determining the susceptibility to C4 delaminations (white bumps) are the effective modulus of the low-K levels in the BEOL stack and the thickness of the upper level in the stack that are built in an oxide dielectric. A simple effective spring model is developed to estimate the impact of metal loading at the via and line levels of interconnect structure on the effective modulus of the low-K dielectric stack. The importance of the effective modulus as a parameter controlling white bump formation is confirmed using a purpose built chip in which the effective modulus is modulated in each corner of the chip. Based on the observations from chip joining experiments it is demonstrated that failng BEOL structures can be differentiated from safe structures using a fail/safe map that is constructed using the effective modulus of the low-K levels and the thickness of the oxide levels as the two axes of the map.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121439536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Combined Vramp and TDDB analysis for gate oxide reliability assessment and screening 结合Vramp和TDDB分析栅极氧化物可靠性评估和筛选

2015 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2015-10-01 DOI: 10.1109/IIRW.2015.7437087

T. Kopley, M. Ring, C. Choi, J. Colbath

引用次数: 8

Memory yield and lifetime estimation considering aging errors 考虑老化误差的存储器产率和寿命估计

2015 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2015-10-01 DOI: 10.1109/IIRW.2015.7437085

Dae-Hyun Kim, L. Milor

引用次数: 7

Extraction of interface and border traps in beyond-Si devices by accounting for generation and recombination in the semiconductor 通过计算半导体中的生成和重组来提取超硅器件中的界面和边界陷阱

2015 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2015-10-01 DOI: 10.1109/IIRW.2015.7437065

G. Sereni, L. Larcher

引用次数: 1

Aging model challenges in deeply scaled tri-gate technologies 老化模型对深度缩放三栅极技术的挑战

2015 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2015-10-01 DOI: 10.1109/IIRW.2015.7437067

S. Ramey, Y. Lu, I. Meric, S. Mudanai, S. Novak, C. Prasad, J. Hicks

引用次数: 14

Charge feedback mechanisms at forward threshold voltage stress in GaN/AlGaN HEMTs GaN/AlGaN hemt中正向阈值电压应力下的电荷反馈机制

2015 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2015-10-01 DOI: 10.1109/IIRW.2015.7437064

A. Grill, G. Rzepa, P. Lagger, C. Ostermaier, H. Ceric, T. Grasser

引用次数: 4

A sampling approach for efficient BEOL TDDB assessment 有效评估BEOL TDDB的抽样方法

2015 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2015-10-01 DOI: 10.1109/IIRW.2015.7437066

A. Kim, C. Christiansen, Baozhen Li, E. Wu, P. McLaughlin

{"title":"A sampling approach for efficient BEOL TDDB assessment","authors":"A. Kim, C. Christiansen, Baozhen Li, E. Wu, P. McLaughlin","doi":"10.1109/IIRW.2015.7437066","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437066","url":null,"abstract":"As semiconductor manufacturing process becomes increasingly complex in advanced technologies, time-to-fail characteristics of BEOL TDDB are often significantly affected by within-wafer process variations, especially in early development stages. With the presence of such an effect, an accurate estimation of TDDB model parameters becomes difficult and sometimes erroneous values can be observed, which may lead to an incorrect conclusion. In order to minimize an artifact of process variation effect on TDDB model parameters, we propose and demonstrate a practical approach of ramped-voltage sample screening followed by grouping of unstressed clone samples for TDDB stresses and determination of voltage stress sequence on samples with a dynamically generated stress wafermap instead of using a predetermined checkerboard pattern wafermap. It is also demonstrated that the proposed approach can help greatly improve the accuracy of long-term TDDB stress results, without invoking large sample studies. An example will be given with this sampling approach how a voltage acceleration parameter can be affected depending on the choice of samples.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114399887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

On the temperature behavior of hot-carrier degradation 热载流子降解的温度行为研究

2015 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2015-10-01 DOI: 10.1109/IIRW.2015.7437088

S. Tyaginov, M. Jech, P. Sharma, J. Franco, B. Kaczer, T. Grasser

引用次数: 1

Further understandings on impacts of La incorporation in HfSiON/TiN nFETs through comprehensive random telegraph noise characterizations 通过综合随机电报噪声表征，进一步了解La掺入对HfSiON/TiN非场效应管的影响

2015 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2015-10-01 DOI: 10.1109/IIRW.2015.7437061

Jiezhi Chen, Y. Mitani

引用次数: 0

Influence of MOSFET geometry on the statistical distribution of NBTI induced parameter degradation MOSFET几何形状对NBTI诱导参数退化统计分布的影响

2015 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 2015-10-01 DOI: 10.1109/IIRW.2015.7437073

C. Schlunder, F. Proebster, J. Berthold, W. Gustin, H. Reisinger

{"title":"Influence of MOSFET geometry on the statistical distribution of NBTI induced parameter degradation","authors":"C. Schlunder, F. Proebster, J. Berthold, W. Gustin, H. Reisinger","doi":"10.1109/IIRW.2015.7437073","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437073","url":null,"abstract":"NBTI parameter degradation of MOSFETs shows a statistical variation. The distribution of the threshold voltage Vth after NBTI stress originates from a convolution of the distribution of the virgin devices together with the additional distribution of the NBTI degradation itself. The variability of the Vth (and other electrical parameters) of the virgin devices bases on process induced fluctuations of dopant atoms, oxide thickness, channel length, etc. The dependence on the transistor size is proven by several publications [e.g. 1,2]. The variability of the NBTI parameter degradation itself and the convolution is not fully understood yet and need further investigation. In this paper we investigate the dependency of the NBTI variability of Vth on the transistor size and geometry. For the necessary statistical relevance we perform NBTI stress experiments with the help of a smart array test-structure at a large amount of pMOS devices with various geometries. We show that the variability of pMOSFETs after NBTI depends not only on the size of the active area (w×l) but also on its geometry (w/l).","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129392075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6