Wafer level test arrays with simple BIST to expedite process development for circuit reliability

Abstract

Conventional time consuming methodology and idealistic stress conditions are no longer satisfactory under fierce competition between advanced technology development approaches. In this paper, the effectiveness of test arrays with simple built-in self-test (BIST) design in FinFET high-k/metal gate (HK/MG) technology have been demonstrated through three experiments performed early in the process development cycle, before products were available to drive yield and process improvements. Early warnings of potential circuit level quality and reliability risk could save several major detours for technology advancement.