IET Circuits Devices Syst.最新文献_第6页

Battery-less non-contact temperature measurement system powered by energy harvesting from intentional human action 无电池非接触式温度测量系统，由能量收集供电，从有意的人类行为

IET Circuits Devices Syst. Pub Date : 2015-04-09 DOI: 10.1049/iet-cds.2013.0437

D. Alghisi, M. Ferrari, V. Ferrari

引用次数: 7

Coulomb blockade in PtSi/porous Si Schottky barrier as a two-dimensional multi-tunnelling junction PtSi/多孔Si肖特基势垒中的库仑阻滞作为二维多隧穿结

IET Circuits Devices Syst. Pub Date : 2015-03-20 DOI: 10.1049/iet-cds.2013.0475

A. Erfanian, H. Mehrara, F. Raissi, M. Khaje

引用次数: 2

Radio-frequency transport Electromagnetic Properties of chemical vapour deposition graphene from direct current to 110 MHz 化学气相沉积石墨烯在直流至110 MHz范围内的射频输运电磁特性

IET Circuits Devices Syst. Pub Date : 2015-02-02 DOI: 10.1049/iet-cds.2014.0204

S. Awan, G. Pan, Laith M. Al Taan, Bing-Jing Li, N. Jamil

{"title":"Radio-frequency transport Electromagnetic Properties of chemical vapour deposition graphene from direct current to 110 MHz","authors":"S. Awan, G. Pan, Laith M. Al Taan, Bing-Jing Li, N. Jamil","doi":"10.1049/iet-cds.2014.0204","DOIUrl":"https://doi.org/10.1049/iet-cds.2014.0204","url":null,"abstract":"The authors report measurement of the radio-frequency (RF) transport electromagnetic properties of chemical vapour deposition graphene over the direct current (DC) to 110 MHz frequency range at room temperature. Graphene on Si/SiO2 substrate was mounted in a shielded four terminal-pair (4TP) adaptor which enabled direct connection to a calibrated precision impedance analyser for measurements. Good agreement is observed for the DC four-probe resistance and the 4TP resistance at 40 Hz, both yielding R ≈ 104 Ω. In general, the apparent graphene channel electromagnetic properties are found to be strongly influenced by the substrate parasitic capacitance and resistance, particularly for high-frequencies f > 1 MHz. A phenomenological lumped-parameter equivalent circuit model is presented which matches the frequency response of the graphene 4TP impedance device over approximately seven decades of the frequency range of the applied transport alternating current. Based on this model, it is shown for the first time, that the intrinsic graphene channel resistance of the 4TP device is ‘frequency-independent’ with R G ≃ 105 Ω or sheet resistance of approximately 182 Ω/□. The parasitic substrate impedance of the device is found to be R P ≃ 2.2 Ω and C P ≃ 600 pF. These results suggest that our new RF 4TP method is in good agreement with the conventional DC four-probe method for measuring the intrinsic sheet resistance of single-atom thick materials and could potentially open up new applications in RF electronics, AC quantum Hall effect metrology and sensors based on graphene 4TP devices operating over a broad range of frequencies.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130588694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Origin of 1/f noise in graphene produced for large-scale applications in electronics 用于电子产品大规模应用的石墨烯中1/f噪声的来源

IET Circuits Devices Syst. Pub Date : 2015-02-02 DOI: 10.1049/iet-cds.2014.0069

V. Kochat, Anindita Sahoo, A. N. Pal, Sneha Eashwer, Gopalakrishnan Ramalingam, A. Sampathkumar, R. Tero, T. V. Thu, S. Kaushal, H. Okada, A. Sandhu, S. Raghavan, A. Ghosh

引用次数: 9

Graphene oxide-based non-volatile organic field effect memory transistors 基于氧化石墨烯的非挥发性有机场效应存储器晶体管

IET Circuits Devices Syst. Pub Date : 2015-01-23 DOI: 10.1049/iet-cds.2014.0064

Homod S. Alaabdlqader, A. Sleiman, P. Sayers, M. Mabrook

引用次数: 9

Thermal properties of graphene and few-layer graphene: applications in electronics 石墨烯和少层石墨烯的热性能:在电子学中的应用

IET Circuits Devices Syst. Pub Date : 2015-01-08 DOI: 10.1049/iet-cds.2014.0093

Zhong Yan, D. Nika, A. Balandin

引用次数: 90

Fractal butterflies of Dirac fermions in monolayer and bilayer graphene 单层和双层石墨烯中狄拉克费米子的分形蝴蝶

IET Circuits Devices Syst. Pub Date : 2014-08-19 DOI: 10.1049/iet-cds.2014.0275

T. Chakraborty, V. Apalkov

{"title":"Fractal butterflies of Dirac fermions in monolayer and bilayer graphene","authors":"T. Chakraborty, V. Apalkov","doi":"10.1049/iet-cds.2014.0275","DOIUrl":"https://doi.org/10.1049/iet-cds.2014.0275","url":null,"abstract":"Bloch electrons in a perpendicular magnetic field exhibit unusual dynamics that has been studied for more than half a century. The single-electron energy spectrum of this system, the Hofstadter butterfly has been the subject of theoretical and experimental investigations for the past two decades. Experimental observation of these unusual spectra in semiconductor nanostructures, however, met with only limited success. The fractal nature of the butterfly spectrum was finally observed in 2013, thanks to the unique electronic properties of graphene. Here, the authors present an overview of the theoretical understanding of Hofstadter butterflies in monolayer and bilayer graphene. First, they briefly discuss the energy spectra in conventional semiconductor systems. The electronic properties of monolayer and bilayer graphene are then presented. Theoretical background on the Moire pattern in graphene and its application in the magnetoconductance probe that resulted in graphene butterflies are explained. They have also touched upon the important role of electron–electron interaction in the butterfly pattern in graphene. Experimental efforts to investigate this aspect of fractal butterflies have just begun. They conclude by discussing the future prospects of butterfly search, especially for interacting Dirac fermions in graphene.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133408169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Digital calibration technique using a signed counter for charge pump mismatch in phase-locked loops 锁相环中电荷泵失配的带符号计数器数字校准技术

IET Circuits Devices Syst. Pub Date : 2013-11-01 DOI: 10.1049/iet-cds.2013.0011

Chan-Hui Jeong, Kyu-Young Kim, Chan-Keun Kwon, H. Kim, Soo-Won Kim

引用次数: 9

Dual-band quadrature voltage-controlled oscillator using differential inner-diamond-structure switchable inductor 采用差动内菱形结构可开关电感的双频正交压控振荡器

IET Circuits Devices Syst. Pub Date : 2013-11-01 DOI: 10.1049/iet-cds.2013.0098

P. Tsai, Tzuen-Hsi Huang, Yu-Ting Chen

引用次数: 5

Scheduling-scheme and parallel structure for multi-level lifting two-dimensional discrete wavelet transform without using frame-buffer 不使用帧缓冲的多级提升二维离散小波变换调度方案及并行结构

IET Circuits Devices Syst. Pub Date : 2013-11-01 DOI: 10.1049/iet-cds.2012.0398

B. K. Mohanty, Anurag Mahajan

{"title":"Scheduling-scheme and parallel structure for multi-level lifting two-dimensional discrete wavelet transform without using frame-buffer","authors":"B. K. Mohanty, Anurag Mahajan","doi":"10.1049/iet-cds.2012.0398","DOIUrl":"https://doi.org/10.1049/iet-cds.2012.0398","url":null,"abstract":"In this paper, we have proposed a novel scheduling scheme for generating continuous input-blocks for the succeeding processing units of parallel structure to achieve 100% hardware utilisation efficiency (HUE) without block folding. Based on the proposed scheme, we have derived a parallel and pipeline structure for multilevel lifting two-dimensional discrete wavelet transform (DWT). The proposed structure involves regular data-flow and does not require frame-buffer, and calculates DWT levels concurrently. A theoretical comparison shows that the proposed structure for\u0000 J \u0000= 2 involves 1.25 times more multipliers and adders, 2\u0000 N \u0000more registers than those of existing folded block-based structure and offers 1.25 times higher throughput, where\u0000 N \u0000is the input-image width. Compared with similar existing parallel structure, the proposed structure requires the same number of multipliers and adders, 2.125\u0000 N \u0000less registers and offers the same throughput rate. Application specific integrated circuit synthesis result shows that the core of the proposed structure for 2-level DWT and image size (512 × 512) involves 41% less area-delay-product and 36% less energy-per-image than those of similar existing parallel structure.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117704783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2