Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)最新文献_第7页

A CMOS even harmonic mixer with current reuse for low power applications 低功耗应用的CMOS均匀谐波混频器电流复用

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013307

Ming-Feng Huang, Shuenn-Yuh Lee, C. Kuo

引用次数: 9

A CPL-based dual supply 32-bit ALU for sub 180 nm CMOS technologies 基于cpld的双电源32位ALU，适用于180nm以下的CMOS技术

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013298

B. Chatterjee, M. Sachdev, R. Krishnamurthy

引用次数: 16

Experimental measurement of a novel power gating structure with intermediate power saving mode 一种新型中间节电电源门控结构的实验测量

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013246

Suhwan Kim, S. Kosonocky, D. Knebel, K. Stawiasz

引用次数: 84

Approaches to run-time and standby mode leakage reduction in global buses 减少全局总线运行和待机模式泄漏的方法

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013285

R. Rao, K. Agarwal, D. Sylvester, Richard B. Brown, K. Nowka, S. Nassif

引用次数: 17

Low-power carry-select adder using adaptive supply voltage based on input vector patterns 基于输入矢量模式的自适应供电电压的低功耗进位选择加法器

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013312

Hiroaki Suzuki, Woopyo Jeong, K. Roy

引用次数: 20

A new algorithm for improved VDD assignment in low power dual VDD systems 低功耗双VDD系统中改进VDD分配的新算法

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013287

S. Kulkarni, A. Srivastava, D. Sylvester

引用次数: 67

Microarchitectural power modeling techniques for deep sub-micron microprocessors 深亚微米微处理器的微架构功率建模技术

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013290

N. Kim, Taeho Kgil, V. Bertacco, T. Austin, T. Mudge

{"title":"Microarchitectural power modeling techniques for deep sub-micron microprocessors","authors":"N. Kim, Taeho Kgil, V. Bertacco, T. Austin, T. Mudge","doi":"10.1145/1013235.1013290","DOIUrl":"https://doi.org/10.1145/1013235.1013290","url":null,"abstract":"The need to perform early design studies that combine architectural simulation with power estimation has become critical as power has become a design constraint whose importance has moved to the fore. To satisfy this demand several microarchitectural power simulators have been developed around SimpleScalar, a widely used microarchitectural performance simulator They have proven to be very useful at providing insights into power/performance trade-offs. However, they are neither parameterized nor technology scalable. In this paper, we propose more accurate parameterized power modeling techniques reflecting the actual technology parameters as well as input switching-events for memory and execution units. Compared to HSPICE, the proposed techniques show 93% and 91% accuracies for those blocks, but with a much faster simulation time. We also propose a more realistic power modeling technique for external I/O. In general, our approach includes more detailed microarchitectural and circuit modeling than has been the case in earlier simulators, without incurring a significant simulation time overhead - it can be as small as a few percent.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130736818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes 一种适用于电压模式数少的复杂soc的高效电压缩放算法

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013326

B. Gorjiara, N. Bagherzadeh, P. Chou

{"title":"An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes","authors":"B. Gorjiara, N. Bagherzadeh, P. Chou","doi":"10.1145/1013235.1013326","DOIUrl":"https://doi.org/10.1145/1013235.1013326","url":null,"abstract":"Increasing demand for larger high-performance applications requires developing more complex systems with hundreds of processing cores on a single chip. To allow dynamic voltage scaling in each on-chip core individually, many on-chip voltage regulators must be used. However, the limitations in implementation of on-chip inductors can reduce the efficiency, accuracy and the number of voltage modes generated by regulators. Therefore the future voltage scheduling algorithms must be efficient, even in the presence of few voltage modes; and fast, in order to handle complex applications. Techniques proposed to date need many fine-grained voltage modes to produce energy efficient results and their quality degrades significantly as the number of modes decreases. This paper presents a new technique called Adaptive Stochastic Gradient Voltage and Task Scheduling (ASG-VTS) that quickly generates very energy efficient results irrespective of the number of available voltage modes. The results of comparing our algorithm to the most efficient approaches (RVS and EE-GLSA) show that in the presence of only four valid modes, the ASG-VTS saves up to 26% and 33% more energy. On the other hand, other approaches require at least ten modes to reach the same level of energy saving that ASG-VTS achieves with only four modes. Therefore our algorithm can also be used to explore and minimize the number of required voltage levels in the system.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133988625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Understanding the energy efficiency of simultaneous multithreading 了解同步多线程的能源效率

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013251

Yingmin Li, D. Brooks, Zhigang Hu, K. Skadron, P. Bose

引用次数: 54

Power-optimal pipelining in deep submicron technology 深亚微米技术中的功率优化流水线

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI: 10.1145/1013235.1013291

Seongmoo Heo, K. Asanović

{"title":"Power-optimal pipelining in deep submicron technology","authors":"Seongmoo Heo, K. Asanović","doi":"10.1145/1013235.1013291","DOIUrl":"https://doi.org/10.1145/1013235.1013291","url":null,"abstract":"This paper explores the effectiveness of pipelining as a power saving tool, where the reduction in logic depth per stage is used to reduce supply voltage at a fixed clock frequency. We examine power-optimal pipelining in deep submicron technology, both analytically and by simulation. Simulation uses a 70 nm predictive process with a fanout-of-four inverter chain model including input/output flipflops, and results are shown to match theory well. The simulation results show that power-optimal logic depth is 6 to 8 FO4 and optimal power saving varies from 55 to 80% compared to a 24 FO4 logic depth, depending on threshold voltage, activity factor, and presence of clock-gating. We decompose the power consumption of a circuit into three components, switching power, leakage power, and idle power, and present the following insights into power-optimal pipelining. First, power-optimal logic depth decreases and optimal power savings increase for larger activity factors, where switching power dominates over leakage and idle power. Second, pipelining is more effective with lower threshold voltages at high activity factors, but higher threshold voltages give better results at lower activity factors where leakage current dominates. Lastly, clock-gating enables deeper pipelining and more power saving because it reduces timing element overhead when the activity factor is low.","PeriodicalId":120002,"journal":{"name":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122766830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 31