A new algorithm for improved VDD assignment in low power dual VDD systems

Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758) Pub Date : 2004-08-09 DOI:10.1145/1013235.1013287

S. Kulkarni, A. Srivastava, D. Sylvester

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引用次数: 67

Abstract

We present the first in-depth study of the two existing algorithms namely, Clustered Voltage Scaling (CVS) and Extended Clustered Voltage Scaling (ECVS), used for assigning the voltage supply to gates in integrated circuits having dual power supplies. We present a comparison of the achievable power savings using these algorithms on various benchmark circuits and first point out that ECVS does provide appreciably larger power improvements compared to CVS. We then provide a new algorithm based on ECVS that further improves the power savings by efficient assignment of the power supplies to the gates. Our new algorithm provides up to 66% power reduction and improves the power savings by up to 28% and 13% with respect to CVS and ECVS respectively. Furthermore, since level conversion is an essential component of dual power supply systems we also present the first circuit-specific sensitivity study of achievable power savings to the energy and delay penalties imposed by level conversion.

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低功耗双VDD系统中改进VDD分配的新算法

我们首次深入研究了现有的两种算法，即聚类电压缩放(CVS)和扩展聚类电压缩放(ECVS)，用于将电压分配给具有双电源的集成电路中的门。我们比较了在各种基准电路上使用这些算法可实现的功耗节约，并首先指出，与CVS相比，ECVS确实提供了明显更大的功耗改进。然后，我们提供了一种基于ECVS的新算法，通过有效地将电源分配到门，进一步提高了功耗节约。与CVS和ECVS相比，我们的新算法提供了高达66%的功耗降低，并分别提高了28%和13%的功耗节约。此外，由于电平转换是双电源系统的重要组成部分，我们还提出了第一个电路特定的灵敏度研究，研究可实现的功率节约对电平转换施加的能量和延迟惩罚的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)

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