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27th ACM/IEEE Design Automation Conference最新文献

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Waveform moment methods for improved interconnection analysis 改进互连分析的波形矩法
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1109/DAC.1990.114891
S. McCormick, Jonathan Allen
{"title":"Waveform moment methods for improved interconnection analysis","authors":"S. McCormick, Jonathan Allen","doi":"10.1109/DAC.1990.114891","DOIUrl":"https://doi.org/10.1109/DAC.1990.114891","url":null,"abstract":"A circuit analysis program is described aimed at quickly solving linear interconnection circuits with inductance and coupling. It computes circuit responses to varying degrees of detail, varying from a simple Elmore delay to a good waveform estimate. The algorithms are based on a new moment polynomial nodal analysis (MPNA) technique that solves for a circuit response with nodal analysis matrix techniques. Allowable circuit forms are much more flexible than for existing Elmore delay algorithms. Large networks or distributed lines can be reduced to a form of transfer function that can subsequently be analyzed much more efficiently with the waveform moment methods.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125169369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Distributed and parallel demand driven logic simulation 分布式和并行需求驱动的逻辑仿真
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1145/123186.123348
Krishnamurthy Subramanian, M. Zargham
{"title":"Distributed and parallel demand driven logic simulation","authors":"Krishnamurthy Subramanian, M. Zargham","doi":"10.1145/123186.123348","DOIUrl":"https://doi.org/10.1145/123186.123348","url":null,"abstract":"Based on a demand-driven approach, distributed and parallel simulation algorithms are proposed. Demand-driven simulation tries to minimize a number of component computations by performing only those required for the watched output requests. For a specific output value request the required input line values are requested from the related component. The authors present a distributed demand-driven algorithm with an infinite memory requirement (but still the memory required by each process is not greater than that of sequential demand-driven simulation), and a parallel demand-driven simulation with reduced memory requirement. In these algorithms, each component is assigned a logical process.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"2673 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128274053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An entropy measure for the complexity of multi-output Boolean functions 多输出布尔函数复杂度的熵测度
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1145/123186.123282
K. Cheng, V. Agrawal
{"title":"An entropy measure for the complexity of multi-output Boolean functions","authors":"K. Cheng, V. Agrawal","doi":"10.1145/123186.123282","DOIUrl":"https://doi.org/10.1145/123186.123282","url":null,"abstract":"Entropy measures are examined in view of the current logic synthesis methodology. The complexity of a Boolean function can be expressed in terms of computational work. Experimental data are presented in support of the entropy definition of computational work based upon the input-output description of a Boolean function. These data show a linear relationship between the computational work and the average number of literals in a multilevel implementation. The investigation includes single-output and multioutput function with and without don't care states. The experiments conducted on a large number of randomly generated functions showed that the effect of don't cares is to reduce the computational work. For several finite state machine benchmarks, the computational work gave a good estimate of the size of the circuit. Circuit delay is shown to have a nonlinear relationship to the computational work.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127495261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 70
Extension of the critical path tracing algorithm 关键路径跟踪算法的扩展
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1109/DAC.1990.114947
T. Ramakrishnan, L. Kinney
{"title":"Extension of the critical path tracing algorithm","authors":"T. Ramakrishnan, L. Kinney","doi":"10.1109/DAC.1990.114947","DOIUrl":"https://doi.org/10.1109/DAC.1990.114947","url":null,"abstract":"Critical path tracing (CPT) is an approximate algorithm used for fast fault simulation, as part of test generation algorithms. It partitions the circuit to be simulated into fanout free regions in order to simplify decisions regarding the propagation of logic signal changes through the circuit. Presented are concepts that result in faster decision making than in CPT for many combinations of input changes. After true value simulation, improved critical path tracing (ICPT) does a more extensive classification of lines than CPT does. This finer classification determines propagation of fault effects without fault simulation in many cases where CPT may require fault simulation. The increase in execution time to incorporate the improvements is insignificant compared to the savings in simulation time for many input vectors.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125524655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Analysis and design of latch-controlled synchronous digital circuits 锁存控制同步数字电路的分析与设计
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1109/DAC.1990.114839
K. Sakallah, T. Mudge, K. Olukotun
{"title":"Analysis and design of latch-controlled synchronous digital circuits","authors":"K. Sakallah, T. Mudge, K. Olukotun","doi":"10.1109/DAC.1990.114839","DOIUrl":"https://doi.org/10.1109/DAC.1990.114839","url":null,"abstract":"A new formulation of the timing constraintss for latch-controlled synchronous digital circuits is presented. The authors show that the constraints are mildly nonlinear, and prove the equivalence of the nonlinear optimal cycle time calculation problem to an associated and simpler linear programming (LP) problem. An LP-based algorithm is presented which is guaranteed to obtain the optimal cycle time for arbitrary circuits controlled by a general class of multi-phase overlapped clocks. An initial implementation of this LP-based solution procedure is illustrated for two example circuits.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126833115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 123
MHERTZ: a new optimization algorithm for floorplanning and global routing MHERTZ:一种新的平面规划和全局路由优化算法
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1109/DAC.1990.114838
D. Brasen, M. Bushnell
{"title":"MHERTZ: a new optimization algorithm for floorplanning and global routing","authors":"D. Brasen, M. Bushnell","doi":"10.1109/DAC.1990.114838","DOIUrl":"https://doi.org/10.1109/DAC.1990.114838","url":null,"abstract":"Timing-driven placement is essential for full-custom VLSI, gallium arsenide, and ECL circuits to meet wire timing constraints. A new macro/custom cell floorplanner and global router, called MHERTZ, is described. It meets wire timing constraints by using force-directed cost functions in multistart and simulated annealing (SA) optimization algorithms. MHERTZ also prevents wire coupling, meets specified chip aspect ratios, and produces smaller floorplans than TIMBERWOLFMC.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134543817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
The influences of fault type and topology on fault model performance and the implications to test and testable design 故障类型和拓扑对故障模型性能的影响及其对测试和可测试性设计的启示
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1109/DAC.1990.114938
K. Butler, M. R. Mercer
{"title":"The influences of fault type and topology on fault model performance and the implications to test and testable design","authors":"K. Butler, M. R. Mercer","doi":"10.1109/DAC.1990.114938","DOIUrl":"https://doi.org/10.1109/DAC.1990.114938","url":null,"abstract":"A new method, difference propagation, is proposed to analyze fault models in combinational circuits. It propagates Boolean functional information represented by ordered binary decision diagrams. Results are presented concerning exact detectabilities and syndromes for a set of benchmark circuits. The data suggest answers to open questions in CAD and represent the first data of this type for bridging faults. The information is shown to affect testable design, as well as test generation.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131475055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
An optimal algorithm for floorplan area optimization 平面面积优化的一种最优算法
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1145/123186.123253
Ting-Chi Wang, D. F. Wong
{"title":"An optimal algorithm for floorplan area optimization","authors":"Ting-Chi Wang, D. F. Wong","doi":"10.1145/123186.123253","DOIUrl":"https://doi.org/10.1145/123186.123253","url":null,"abstract":"An optimal algorithm for the VLSI floorplan area optimization problem is presented. The algorithm is an extension of the technique described by L. Stockmeyer (Information and Control, vol.59, p.91-101, 1983). Experimental results indicate that this algorithm pruned a very large number of redundant implementations. In addition, since the algorithm basically exploits the geometric property of the topology of the given floorplan it does not need to depend on the polar dual graphs to calculate the longest paths. Consequently it is able to run more efficiently than the branch-and-bound algorithm.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114082387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 92
Automatic test generation using quadratic 0-1 programming 自动测试生成使用二次0-1编程
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1109/DAC.1990.114935
S. Chakradhar, V. Agrawal, M. Bushnell
{"title":"Automatic test generation using quadratic 0-1 programming","authors":"S. Chakradhar, V. Agrawal, M. Bushnell","doi":"10.1109/DAC.1990.114935","DOIUrl":"https://doi.org/10.1109/DAC.1990.114935","url":null,"abstract":"In an unconventional digital circuit modeling technique using neural nets proposed by the authors, the relationship between the input and output signal states of a logic gate is expressed through an energy function such that the minimum-energy states correspond to the gate's logic function. Based on these unconventional models, automatic test generation (ATG) was formulated as an energy minimization problem. Although energy minimization is as hard as test generation, the new approach has two advantages. Since the circuit function is mathematically expressed, operations research techniques like linear and nonlinear programming can be applied to test generation. The noncausal form of the model makes parallel processing possible. The authors present a new discrete nonlinear programming technique for ATG. Discussed are several easily parallelizable speedup techniques using the transitive closure and other graph properties. Preliminary results on combinational circuits confirm the feasibility of this technique.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124650327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Is redundancy necessary to reduce delay? 是否需要冗余来减少延迟?
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1109/DAC.1990.114859
K. Keutzer, S. Malik, A. Saldanha
{"title":"Is redundancy necessary to reduce delay?","authors":"K. Keutzer, S. Malik, A. Saldanha","doi":"10.1109/DAC.1990.114859","DOIUrl":"https://doi.org/10.1109/DAC.1990.114859","url":null,"abstract":"Logic optimization procedures principally attempt to optimize three criteria: performance, area, and testability. The relationship between area optimization and testability has recently been explored. As to the relationship between performance and testability, experience has shown that performance optimizations can, and do in practice, introduce single stuck-at-fault redundancies into designs. Are these redundancies necessary to increase performance or are they only an unnecessary by-product of performance optimization? The authors give a constructive resolution of this question in the form of an algorithm that takes as input a combinational circuit and returns an irredundant circuit that is as fast. They demonstrate the utility of this algorithm on a well-known circuit, the carry-skip adder, and present a novel irredundant design of that adder. As this algorithm may either increase or decrease circuit area, the authors leave unresolved the question as to whether every circuit has all irredundant circuit that is at least as fast and is of equal or lesser area.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"394 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116020912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 86
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