发布求助
文献互助 智能选刊 最新文献

27th ACM/IEEE Design Automation Conference最新文献

筛选
英文 中文
Performance-driven constructive placement 绩效驱动的建设性安置
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1109/DAC.1990.114837
I. Lin, D. Du
{"title":"Performance-driven constructive placement","authors":"I. Lin, D. Du","doi":"10.1109/DAC.1990.114837","DOIUrl":"https://doi.org/10.1109/DAC.1990.114837","url":null,"abstract":"A new approach to performance-driven placement based on a window concept is presented. Timing constraints are first converted to geometric shapes using the defined windows. A window represents a region in which all the modules along a given path can be placed without degrading the circuit performance. Then a constructive placement process uses the window information to select an unplaced module, and to find all appropriate position for the module. This approach represents a unified way to consider both timing and geometric constraints during the VLSI placement process. The experimental results show that improvement of circuit performance can be achieved by sufficient use of the window information.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115002858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
A hierarchy preserving hierarchical compactor 保留层次结构的层次压缩器
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1109/DAC.1990.114886
D. Marple
{"title":"A hierarchy preserving hierarchical compactor","authors":"D. Marple","doi":"10.1109/DAC.1990.114886","DOIUrl":"https://doi.org/10.1109/DAC.1990.114886","url":null,"abstract":"A one-dimensional IC layout compactor is presented which simultaneously compacts the contents of all cells of the layout hierarchy without changing this hierarchy. The compactor performs both compaction and wire length minimization hierarchically using the power of the Simplex method for linear programs. Compaction of arrays of overlapping cells and symmetry preserving compaction are also handled, since these are special cases of layout hierarchies. Using dedicated simplex algorithms for compaction and wire length minimization, a globally optimal result is produced quickly and efficiently, without the use of protection frames or domains and terminals. The compactor corrects design rule violations, preserves wire widths, and maintains terminal connections automatically. It does not yet introduce jogs in wires automatically. Results are provided for a few CMOS modules, including a ROM and a SRAM core.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116960407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
The VHDL validation suite VHDL验证套件
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1109/DAC.1990.114819
J. Armstrong, C. Cho, Sandeep Shah, C. Kosaraju
{"title":"The VHDL validation suite","authors":"J. Armstrong, C. Cho, Sandeep Shah, C. Kosaraju","doi":"10.1109/DAC.1990.114819","DOIUrl":"https://doi.org/10.1109/DAC.1990.114819","url":null,"abstract":"A validation suite for the IEEE standard VHSIC Hardware Description Language (VHDL) is discussed along with its executive manager. Test points are generated from the VHDL LRM (language reference manual) syntax diagrams and sentences. Each test in the suite contains a test header which is specially formatted and keeps information such as test point, test objective, test result, and test type. The suit executive manager is menu-driven and efficiently classifies the tests based on different criterion defined in the test header. Coverage is defined to measure how closely a VHDL tool covers the LRM and is also computed by the suite executive manager.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114403735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Architecture synthesis of high-performance application-specific processors 高性能应用程序特定处理器的体系结构综合
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1109/DAC.1990.114915
M. Breternitz, John Paul Shen
{"title":"Architecture synthesis of high-performance application-specific processors","authors":"M. Breternitz, John Paul Shen","doi":"10.1109/DAC.1990.114915","DOIUrl":"https://doi.org/10.1109/DAC.1990.114915","url":null,"abstract":"An automated approach, called architecture synthesis, for designing application-specific processors is presented. The key principles of the application-specific processor design (ASPD) methodology include: a semicustom compilation-driven design/implementation approach, the exploitation of fine-grained parallelism for high performance, and the adaptation of datapath topology to the data transfers required by the application. The powerful microcode compilation techniques of percolation scheduling and pipeline scheduling extract and enhance the parallelism in the application object code to generate all optimized specification of the target processor. Implementation optimization is performed to allocate functional units and register files. Graph-coloring algorithms minimize the amount of hardware needed to exploit available parallelism. Data memory employs an organization with multiple banks. Compilation techniques are used to allocate data over the memory banks to enhance parallel access.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116906412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
Logic optimization algorithm by linear programming approach 逻辑优化算法采用线性规划方法
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1145/123186.123299
N. Kageyama, Chihei Miura, Tsuguo Shimizu
{"title":"Logic optimization algorithm by linear programming approach","authors":"N. Kageyama, Chihei Miura, Tsuguo Shimizu","doi":"10.1145/123186.123299","DOIUrl":"https://doi.org/10.1145/123186.123299","url":null,"abstract":"A new logic synthesis algorithm for reducing the delay time with the least increase of gate is presented. This algorithm uses a linear programming approach and makes it possible for delay and gate optimization to be achieved simultaneously from the global point of view. Therefore, this new algorithm prevents the generation of redundant logic arising from the delay time improvement, which is a weakness of the conventional method.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132230283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Shared binary decision diagram with attributed edges for efficient Boolean function manipulation 具有属性边的共享二进制决策图，用于有效的布尔函数操作
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1109/DAC.1990.114828
S. Minato, N. Ishiura, S. Yajima
{"title":"Shared binary decision diagram with attributed edges for efficient Boolean function manipulation","authors":"S. Minato, N. Ishiura, S. Yajima","doi":"10.1109/DAC.1990.114828","DOIUrl":"https://doi.org/10.1109/DAC.1990.114828","url":null,"abstract":"The efficiency of Boolean function manipulation depends on the form of representation of Boolean functions. Binary decision diagrams (BDDs) are graph representations proposed by S.B. Akers (1978) and R.E. Bryant (1985). BDDs have some properties which can be used to enable efficient Boolean function manipulation. The authors describe a technique of more efficient Boolean function manipulation that uses shared binary decision diagrams (SBDDs) with attributed edges. The implements include an ordering algorithm of input variables and a method of handling 'don't care'. A Boolean function manipulator using the above methods is developed and it is shown that the manipulator is very efficient in terms of speed and storage.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134231692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 454
SKILL: a CAD system extension language 技能:CAD系统扩展语言
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1109/DAC.1990.114865
T. J. Barnes
{"title":"SKILL: a CAD system extension language","authors":"T. J. Barnes","doi":"10.1109/DAC.1990.114865","DOIUrl":"https://doi.org/10.1109/DAC.1990.114865","url":null,"abstract":"SKILL is a programming language that supports both command entry and procedural customization in the Opus design framework. The author examines the requirements that motivate the provision of a programming language available to the user and describes some of the technical characteristics of the language design and implementation. Experience with the language is described and a number of programming examples are presented.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131904064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
Datapath generator based on gate-level symbolic layout 基于门级符号布局的数据路径生成器
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1145/123186.123314
Nobu Matsumoto, Y. Watanabe, K. Usami, Y. Sugeno, H. Hatada, S. Mori
{"title":"Datapath generator based on gate-level symbolic layout","authors":"Nobu Matsumoto, Y. Watanabe, K. Usami, Y. Sugeno, H. Hatada, S. Mori","doi":"10.1145/123186.123314","DOIUrl":"https://doi.org/10.1145/123186.123314","url":null,"abstract":"A data-path generator that generates high-density LSI mask layouts equivalent to hand-crafted ones is described. An entry of the generator is a hierarchical symbolic layout at the gate level. The bit-and-row-slicing technique is a key feature for realizing large-size and high-density data-path generation. A 21 K-transistor data-path whose density is 5.64 KTr/mm/sup 2/, greater than the 5.38 KTr/mm/sup 2/ of a hand-crafted datapath, was generated using 1- mu m CMOS technology.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116438176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A hardware implementation of gridless routing based on content addressable memory 一种基于内容可寻址存储器的无网格路由的硬件实现
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1109/DAC.1990.114933
M. Sato, K. Kubota, T. Ohtsuki
{"title":"A hardware implementation of gridless routing based on content addressable memory","authors":"M. Sato, K. Kubota, T. Ohtsuki","doi":"10.1109/DAC.1990.114933","DOIUrl":"https://doi.org/10.1109/DAC.1990.114933","url":null,"abstract":"A new gridless router accelerated by content addressable memory (CAM) is presented. A gridless version of the line-expansion algorithm is implemented, which always finds a path if one exists. The router runs in linear time by means of the CAM-based accelerator. Experimental results show that the more obstacles there are in the routing region, the more effective the CAM-based approach is. The CAM-based layout engine provides the flexibility to deal with a variety of geometrical search problems for VLSI design. Another advantage is that complicated coding for sophisticated data structures depending on subproblems is not necessary.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121981797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A fault analysis method for synchronous sequential circuits 同步顺序电路的故障分析方法
27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI: 10.1109/DAC.1990.114950
T. Kuo, Jau-Yien Lee, Jhing-Fa Wang
{"title":"A fault analysis method for synchronous sequential circuits","authors":"T. Kuo, Jau-Yien Lee, Jhing-Fa Wang","doi":"10.1109/DAC.1990.114950","DOIUrl":"https://doi.org/10.1109/DAC.1990.114950","url":null,"abstract":"A new fault analysis method for synchronous sequential circuits is presented. Using the iterative array method, extended forward propagation and backward implication are performed, based on the observed values at primary outputs, to deduce the actual values of each line to determine its fault status. Any stuck fault can be identified, even in a circuit without any initialization sequence. A fault which is covered is tested unconditionally; thus the results obtained would not be invalidated in the presence of tested or untestable lines. Examples are given to demonstrate the ability of the method.<<ETX>>","PeriodicalId":118552,"journal":{"name":"27th ACM/IEEE Design Automation Conference","volume":"225 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123982882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信