Analysis and design of latch-controlled synchronous digital circuits

Abstract

A new formulation of the timing constraintss for latch-controlled synchronous digital circuits is presented. The authors show that the constraints are mildly nonlinear, and prove the equivalence of the nonlinear optimal cycle time calculation problem to an associated and simpler linear programming (LP) problem. An LP-based algorithm is presented which is guaranteed to obtain the optimal cycle time for arbitrary circuits controlled by a general class of multi-phase overlapped clocks. An initial implementation of this LP-based solution procedure is illustrated for two example circuits.<>