MHERTZ:一种新的平面规划和全局路由优化算法

27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI:10.1109/DAC.1990.114838

D. Brasen, M. Bushnell

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引用次数: 11

摘要

时序驱动的放置对于全定制VLSI、砷化镓和ECL电路来说是必不可少的，以满足线时序限制。描述了一种新的宏/自定义单元地板规划器和全局路由器，称为MHERTZ。它通过在多启动和模拟退火(SA)优化算法中使用力导向代价函数来满足导线时序约束。MHERTZ还可以防止电线耦合，满足指定的芯片长宽比，并且产生比TIMBERWOLFMC更小的平面图。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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MHERTZ: a new optimization algorithm for floorplanning and global routing

Timing-driven placement is essential for full-custom VLSI, gallium arsenide, and ECL circuits to meet wire timing constraints. A new macro/custom cell floorplanner and global router, called MHERTZ, is described. It meets wire timing constraints by using force-directed cost functions in multistart and simulated annealing (SA) optimization algorithms. MHERTZ also prevents wire coupling, meets specified chip aspect ratios, and produces smaller floorplans than TIMBERWOLFMC.<>

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27th ACM/IEEE Design Automation Conference

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