Automatic test generation using quadratic 0-1 programming

Abstract

In an unconventional digital circuit modeling technique using neural nets proposed by the authors, the relationship between the input and output signal states of a logic gate is expressed through an energy function such that the minimum-energy states correspond to the gate's logic function. Based on these unconventional models, automatic test generation (ATG) was formulated as an energy minimization problem. Although energy minimization is as hard as test generation, the new approach has two advantages. Since the circuit function is mathematically expressed, operations research techniques like linear and nonlinear programming can be applied to test generation. The noncausal form of the model makes parallel processing possible. The authors present a new discrete nonlinear programming technique for ATG. Discussed are several easily parallelizable speedup techniques using the transitive closure and other graph properties. Preliminary results on combinational circuits confirm the feasibility of this technique.<>