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2017 International Conference on High Performance Computing & Simulation (HPCS)最新文献

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Cleaning MapReduce Workflows 清理MapReduce工作流
2017 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2017-07-01 DOI: 10.1109/HPCS.2017.22
Matteo Interlandi, Julien Lacroix, Omar Boucelma, F. Guerra
{"title":"Cleaning MapReduce Workflows","authors":"Matteo Interlandi, Julien Lacroix, Omar Boucelma, F. Guerra","doi":"10.1109/HPCS.2017.22","DOIUrl":"https://doi.org/10.1109/HPCS.2017.22","url":null,"abstract":"Integrity constraints (ICs) such as Functional Dependencies (FDs) or Inclusion Dependencies (INDs) are commonly used in databases to check if input relations obey to certain pre-defined quality metrics. While Data-Intensive Scalable Computing (DISC) platforms such as MapReduce commonly accept as input (semi-structured) data not in relational format, still data is often transformed in key/value pairs when data is required to be re-partitioned; a process commonly referred to as shuffle. In this work, we present a Provenance-Aware model for assessing the quality of shuffled data: more precisely, we capture and model provenance using the PROV-DM W3C recommendation and we extend it with rules expressed à la Datalog to assess data quality dimensions by means of ICs metrics over DISC systems. In this way, data (and algorithmic) errors can be promptly and automatically detected without having to go through a lengthy process of output debugging.","PeriodicalId":115758,"journal":{"name":"2017 International Conference on High Performance Computing & Simulation (HPCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134200803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Efficient Codec for Image Compression Based on Spline Wavelet Transform and Improved SPIHT Algorithm 基于样条小波变换和改进SPIHT算法的高效图像压缩编解码器
2017 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2017-07-01 DOI: 10.1109/HPCS.2017.124
Rania Boujelbene, Y. Jemaa, M. Zribi
{"title":"An Efficient Codec for Image Compression Based on Spline Wavelet Transform and Improved SPIHT Algorithm","authors":"Rania Boujelbene, Y. Jemaa, M. Zribi","doi":"10.1109/HPCS.2017.124","DOIUrl":"https://doi.org/10.1109/HPCS.2017.124","url":null,"abstract":"This paper presents an efficient codec which is based on an optimal spline wavelet transform and an improved Set Partitioning in Hierarchical Trees algorithm. A comparative study of the proposed codec with the existing works using the polynomial spline based transform and the biorthogonal B9/7 which is frequently used in image compression is done. Peak signal-to-noise ratio (PSNR), structural similarity index measure (SSIM) and encoding time are used for evaluation purpose. The obtained results prove the efficiency and the speed of the proposed codec.","PeriodicalId":115758,"journal":{"name":"2017 International Conference on High Performance Computing & Simulation (HPCS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123341661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
The RE-SEARCH ALPS (Research Laboratories in the Alpine Area) Project “阿尔卑斯研究实验室”项目
2017 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2017-07-01 DOI: 10.1109/HPCS.2017.20
F. Guerra, M. Russo, Marco Fontana, Matteo Paganelli, F. Bancilhon, Christian Frisch, Lo c Petit, A. Giorgi, Emanuela Zilio
{"title":"The RE-SEARCH ALPS (Research Laboratories in the Alpine Area) Project","authors":"F. Guerra, M. Russo, Marco Fontana, Matteo Paganelli, F. Bancilhon, Christian Frisch, Lo c Petit, A. Giorgi, Emanuela Zilio","doi":"10.1109/HPCS.2017.20","DOIUrl":"https://doi.org/10.1109/HPCS.2017.20","url":null,"abstract":"The paper describes the RE-SEARCH ALPS project, which aims to gather, consolidate, harmonize and make available to different targets (public and private bodies working at local, regional and national level) data about laboratories, research and innovation centers which are active in particular in the regions of seven countries which constitute the Alpine Area (France, Italy, Switzerland, Austria, Germany, Liechtenstein and Slovenia). The project is complemented with a search engine which allows the users to directly query the dataset and to obtain geo referenced data as result. The data will be properly visualized thanks a visualizer developed in the project. From a research perspective, the project has to address hot and challenging Big Data issues, such as big data integration (to join data sources), entity recognition and linkage in large amount of data (to discover the same Institution represented in different sources), data cleaning and reconciliation (to address issues related to different representation of the same real object). The project has been applied in a call for the cration of Open Datasets promoted by the European Innovation and Networks Executive Agency through the Connecting Europe Facility (CEF) funding instrument. The project has been recently approved (AGREEMENT No INEA/CEF/ICT/A2016/1296967): it lasts two years and will start on July 2017.","PeriodicalId":115758,"journal":{"name":"2017 International Conference on High Performance Computing & Simulation (HPCS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124218704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Fast CUDA-Based Implementation for the Euclidean Distance Transform 基于cuda的欧氏距离变换快速实现
2017 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2017-07-01 DOI: 10.1109/HPCS.2017.123
F. Zampirolli, Leonardo Filipe
{"title":"A Fast CUDA-Based Implementation for the Euclidean Distance Transform","authors":"F. Zampirolli, Leonardo Filipe","doi":"10.1109/HPCS.2017.123","DOIUrl":"https://doi.org/10.1109/HPCS.2017.123","url":null,"abstract":"In Image Processing efficient algorithms are always pursued for applications that use the most advanced hardware architectures. Distance Transform is a classic operation for blurring effects, skeletonizing, segmentation and various other purposes. This article presents two implementations of the Euclidean Distance Transform using CUDA (Compute Unified Device Architecture) in GPU (Graphics Process Unit): of the Meijster's Sequential Algorithm and another is a very efficient algorithm of simple structure. Both using only shared memory. The results presented herein used images of various types and sizes to show a faster run time compared with the best-known implementations in CPU.","PeriodicalId":115758,"journal":{"name":"2017 International Conference on High Performance Computing & Simulation (HPCS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122343744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A Modular-Logarithmic Coprocessor Concept 模对数协处理器概念
2017 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2017-07-01 DOI: 10.1109/HPCS.2017.93
I. Osinin
{"title":"A Modular-Logarithmic Coprocessor Concept","authors":"I. Osinin","doi":"10.1109/HPCS.2017.93","DOIUrl":"https://doi.org/10.1109/HPCS.2017.93","url":null,"abstract":"The paper presents a conceptual design of an IP module of mathematical coprocessor. It consists of a set of processing cores of the same kind which perform single-cycle scalar, or vector operations with real numbers. The processed data is represented in the modular logarithmic format that provides two levels of translating the original numbers, namely: the modular level instead of the conventional positional system and the logarithmic level instead of the floating point format. Owing to this feature a coprocessor has a higher performance, a higher accuracy and a higher level of reliability, as compared to the known analogs. A prototype coprocessor is an FPGA-based IP module. Companies developing general-purpose processors are the target market for this design.","PeriodicalId":115758,"journal":{"name":"2017 International Conference on High Performance Computing & Simulation (HPCS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115320664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Advanced VLSI Circuits Simulation 高级VLSI电路仿真
2017 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2017-07-01 DOI: 10.1109/HPCS.2017.84
Filip Kocina, J. Kunovsky
{"title":"Advanced VLSI Circuits Simulation","authors":"Filip Kocina, J. Kunovsky","doi":"10.1109/HPCS.2017.84","DOIUrl":"https://doi.org/10.1109/HPCS.2017.84","url":null,"abstract":"The paper deals with very accurate and effective simulation of Complementary Metal-Oxide-Semiconductor (CMOS) transistors which are used to construct basic logic gates (inverter, NAND and NOR) and their composites (XOR, AND, OR). The transistors are substituted by a resistor-capacitor (RC) circuit and the circuit is described by a system of differential algebraic equations (DAEs). These equations are numerically solved by the variable-step, variable-order Modern Taylor Series Method (MTSM). The same approach can be used for VLSI simulation — it was implemented by the corresponding author in a general purpose programming language. This approach is faster than the state of the art (SPICE) and uses less memory.","PeriodicalId":115758,"journal":{"name":"2017 International Conference on High Performance Computing & Simulation (HPCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115946612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Post-Quantum Cryptographic Schemes Based on Codes 基于码的后量子密码方案
2017 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2017-07-01 DOI: 10.1109/HPCS.2017.151
M. Baldi
{"title":"Post-Quantum Cryptographic Schemes Based on Codes","authors":"M. Baldi","doi":"10.1109/HPCS.2017.151","DOIUrl":"https://doi.org/10.1109/HPCS.2017.151","url":null,"abstract":"Not all mathematical problems that today are considered hard will remain hard after the advent of quantum computers. In fact, there are some quantum algorithms able to accelerate the solution of some problems that are hard to solve with classical non-quantum computers. Among these, Grover’s algorithm [1] is able to provide a quadratic speedup in the search of an item in a non-ordered list, whereas Shor’s [2] algorithm is even more groundbreaking, since it allows to find the prime factors of an integer in polynomial time.","PeriodicalId":115758,"journal":{"name":"2017 International Conference on High Performance Computing & Simulation (HPCS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121296007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Extending OpenACC for Efficient Stencil Code Generation and Execution by Skeleton Frameworks 通过骨架框架扩展OpenACC以实现高效的模板代码生成和执行
2017 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2017-07-01 DOI: 10.1109/HPCS.2017.110
Alyson D. Pereira, M. Castro, M. Dantas, Rodrigo C. O. Rocha, L. F. Góes
{"title":"Extending OpenACC for Efficient Stencil Code Generation and Execution by Skeleton Frameworks","authors":"Alyson D. Pereira, M. Castro, M. Dantas, Rodrigo C. O. Rocha, L. F. Góes","doi":"10.1109/HPCS.2017.110","DOIUrl":"https://doi.org/10.1109/HPCS.2017.110","url":null,"abstract":"The OpenACC programming model simplifies the programming for accelerator devices such as GPUs. Its abstract accelerator model defines a least common denominator for accelerator devices, thus it cannot represent architectural specifics of these devices without losing portability. Therefore, this general- purpose approach delivers good performance on average, but it misses optimization opportunities for code generation and execution of specific classes of applications. In this paper, we propose OpenACC extensions to enable efficient code generation and execution of stencil applications by parallel skeleton frameworks such as PSkel. Our results show that our stencil extensions may improve the performance of OpenACC in up to 28% and 45% on GPU and CPU, respectively. Moreover, we show that the work-partitioning mechanism offered by the skeleton framework, which splits the computation across CPU and GPU, may improve even further the performance of the applications in up to 18%.","PeriodicalId":115758,"journal":{"name":"2017 International Conference on High Performance Computing & Simulation (HPCS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116930438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Peer-to-Peer Architecture for Detecting Attacks from Network Traffic and Log Data 基于网络流量和日志数据的点对点攻击检测体系结构
2017 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2017-07-01 DOI: 10.1109/HPCS.2017.116
Francesco Folino, G. Folino, L. Pontieri, Pietro Sabatino
{"title":"A Peer-to-Peer Architecture for Detecting Attacks from Network Traffic and Log Data","authors":"Francesco Folino, G. Folino, L. Pontieri, Pietro Sabatino","doi":"10.1109/HPCS.2017.116","DOIUrl":"https://doi.org/10.1109/HPCS.2017.116","url":null,"abstract":"Intrusion detection systems (IDS) support the recognition of attacks, based on the analysis of either network traffic data (Network-based IDS) or application/system logs stored in a host (Host-based IDS). Exploiting heterogeneous data coming from both kinds of sources could be useful to detect coordinated attacks and to reduce the number of false alarms, but poses challenges in terms of both information integration and scalability. In order to foster the development of such a hybrid IDS, we here propose a p2p intrusion detection architecture, which combines different data manipulation/mining techniques and a collaborative ensemble-based learning approach, and allows to incrementally classify attacks by integrating information extracted from both network traffic data and host logs. Preliminary experiments, conducted on real-life dataset, show that the approach is promising.","PeriodicalId":115758,"journal":{"name":"2017 International Conference on High Performance Computing & Simulation (HPCS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125564724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Sampled Antenna Array Digital Beamforming for LTE-Advanced LTE-Advanced采样天线阵列数字波束形成
2017 International Conference on High Performance Computing & Simulation (HPCS) Pub Date : 2017-07-01 DOI: 10.1109/HPCS.2017.51
Mohammad H. Haroun, H. Ayad, Jalal Jomaa, M. Fadlallah, K. Jomaa, M. Cabedo-Fabrés, M. Ferrando-Bataller
{"title":"Sampled Antenna Array Digital Beamforming for LTE-Advanced","authors":"Mohammad H. Haroun, H. Ayad, Jalal Jomaa, M. Fadlallah, K. Jomaa, M. Cabedo-Fabrés, M. Ferrando-Bataller","doi":"10.1109/HPCS.2017.51","DOIUrl":"https://doi.org/10.1109/HPCS.2017.51","url":null,"abstract":"In this paper, a beamforming system for LTE- Advanced based on Array sampling technology is proposed. Antenna Array that has been designed covers LTE mid and high bands. RF multiplexer 8x1 switch has been designed and simulated. The system is composed of agile RF frontend and FPGA digital signal processing unit.","PeriodicalId":115758,"journal":{"name":"2017 International Conference on High Performance Computing & Simulation (HPCS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126723371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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