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2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)最新文献

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4H-SiC MESFET specially designed and fabricated for high temperature integrated circuits 专为高温集成电路设计制造的4H-SiC MESFET
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818829
M. Alexandru, V. Banu, P. Godignon, M. Vellvehí, J. Millán
{"title":"4H-SiC MESFET specially designed and fabricated for high temperature integrated circuits","authors":"M. Alexandru, V. Banu, P. Godignon, M. Vellvehí, J. Millán","doi":"10.1109/ESSDERC.2013.6818829","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818829","url":null,"abstract":"Due to its wide bandgap, 4H-SiC is a potential candidate for developing devices capable to operate at elevated temperatures. Nowadays there is an increasing demand for high temperature circuits for drivers of SiC switches applicable to intelligent power management, automotive industry, intelligent sensors for harsh environment, space and aerospace among others. This paper is presenting high temperature experimental results in the 25°C-300°C temperature range of the 4H-SiC planar-MESFET specially designed and fabricated for high density SiC integrated circuits implementation.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128453950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Threshold voltage extraction techniques and temperature effect in context of global variability in UTBB mosfets 阈值电压提取技术和温度效应在UTBB效应全局变率的背景下
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818852
S. Makovejev, B. K. Esfeh, J. Raskin, D. Flandre, V. Kilchytska, F. Andrieu
{"title":"Threshold voltage extraction techniques and temperature effect in context of global variability in UTBB mosfets","authors":"S. Makovejev, B. K. Esfeh, J. Raskin, D. Flandre, V. Kilchytska, F. Andrieu","doi":"10.1109/ESSDERC.2013.6818852","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818852","url":null,"abstract":"Assessment of global threshold voltage (Vth) variability in advanced silicon-on-insulator devices implies careful selection of a Vth extraction technique as different methods are sensitive to different parameters and effects. Our main focus is on experimental assessment of most widely used techniques, such as constant current, transconductance derivative and recently introduced gm/Id techniques. Some comparison with linear extrapolation methods is also provided. It is shown that gm/Id method, using data near threshold, is less sensitive to cross-impact of short channel effects (i.e. subthreshold slope and drain induced barrier lowering) variability. Therefore this method is preferred for extraction of intrinsic Vth variability without parasitic effects. Temperature evolution of global inter-die parameter variability is assessed for the first time. Possible reasons of slight variability temperature dependence are discussed.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"22 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130463694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Characterization of border traps in III-V MOSFETs using an RF transconductance method 利用射频跨导方法表征III-V型mosfet的边界陷阱
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818817
Sofia Johansson, Jiongjiong Mo, E. Lind
{"title":"Characterization of border traps in III-V MOSFETs using an RF transconductance method","authors":"Sofia Johansson, Jiongjiong Mo, E. Lind","doi":"10.1109/ESSDERC.2013.6818817","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818817","url":null,"abstract":"The significant defect-induced increase in transconductance at high frequencies in some III-V MOSFETs is utilized to reveal the spatial distribution and energy profile of traps in the gate dielectric. The frequency response of the border traps is modeled as a distributed RC network inserted in the small signal model. Surface-channel InGaAs MOSFETs with Al2O3/HfO2 high-k gate dielectric are evaluated; especially the effects of inserting an InP cap layer in the gate stack.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121520505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A novel HfO2-GeS2-Ag based conductive bridge RAM for reconfigurable logic applications 用于可重构逻辑应用的新型HfO2-GeS2-Ag导电桥式RAM
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818869
G. Palma, E. Vianello, O. Thomas, Houcine Oucheikh, S. Onkaraiah, A. Toffoli, C. Carabasse, G. Molas, B. D. Salvo
{"title":"A novel HfO2-GeS2-Ag based conductive bridge RAM for reconfigurable logic applications","authors":"G. Palma, E. Vianello, O. Thomas, Houcine Oucheikh, S. Onkaraiah, A. Toffoli, C. Carabasse, G. Molas, B. D. Salvo","doi":"10.1109/ESSDERC.2013.6818869","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818869","url":null,"abstract":"In this paper, we propose a novel HfO2-GeS2-Ag based Conductive Bridge RAM (CBRAM) device as a promising candidate to replace Flash and SRAM-based configuration memory in reconfigurable logic circuits, such as Field Programmable Gate Arrays (FPGAs). In order to evaluate the feasibility of our new cell for FPGA architectures, 1T-1R CBRAM devices (both isolated and 8×8 matrix) were electrically characterized in a range of logic compatible programming conditions. A resistance ratio (Roff/Ron) of 106 between off/on states, small programming currents (lower than 100 μA) and projected 10 years disturb immunity at 0.04 V are demonstrated. We argue that the optimized cell, integrated in a 1T-2R CBRAM architecture, fits well with the aggressive requirements of a configuration memory because of being non volatile, Back-End-Of-Line (BEOL) compatible and exhibiting sub-200 pA leakage current during read operation.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114436882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Physical understanding of electron mobility in uniaxially strained InGaAs-OI MOSFETs 单轴应变InGaAs-OI mosfet中电子迁移率的物理理解
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818838
Sanghyeon Kim, M. Yokoyama, Y. Ikku, R. Nakane, O. Ichikawa, T. Osada, M. Hata, M. Takenaka, S. Takagi
{"title":"Physical understanding of electron mobility in uniaxially strained InGaAs-OI MOSFETs","authors":"Sanghyeon Kim, M. Yokoyama, Y. Ikku, R. Nakane, O. Ichikawa, T. Osada, M. Hata, M. Takenaka, S. Takagi","doi":"10.1109/ESSDERC.2013.6818838","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818838","url":null,"abstract":"In this paper, we have fabricated uniaxially tensile strained In<sub>0.33</sub>Ga<sub>0.47</sub>As-OI MOSFETs, for the first time, using a lateral strain relaxation technique. A stripe-like line structure was fabricated from biaxially-strained In<sub>0.53</sub>Ga<sub>0.47</sub>As-OI. This structure exhibits the lateral strain relaxation. We have found that μeff in strained In<sub>0.53</sub>Ga<sub>0.47</sub>As-OI MOSFETs decreases with a decrease in the gate width (W<sub>G</sub>) as the mesa width. This mobility behavior can be understood by conduction band minimum (CBM) change due to the lateral strain relaxation.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"264 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115286321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel low temperature 3D wafer stacking technology for high density device integration 面向高密度器件集成的新型低温3D晶圆堆叠技术
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818841
I. Radu, G. Gaudin, W. V. D. Daele, F. Letertre, C. Mazure, L. Cioccio, Thomas Lacave, F. Mazen, Pascal Scheiblin, T. Signamarcheix, S. Cristoloveanu
{"title":"Novel low temperature 3D wafer stacking technology for high density device integration","authors":"I. Radu, G. Gaudin, W. V. D. Daele, F. Letertre, C. Mazure, L. Cioccio, Thomas Lacave, F. Mazen, Pascal Scheiblin, T. Signamarcheix, S. Cristoloveanu","doi":"10.1109/ESSDERC.2013.6818841","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818841","url":null,"abstract":"Low temperature 3D wafer stacking for very high density device integration is achieved using the Smart Cut™ technology and solid phase re-crystallization. Thin silicon PN bi-layers of high quality are transferred onto new handle substrate without exceeding 500°C. The current-voltage characteristics of the intrinsic PN diode are significantly improved by using low temperature solid-phase epitaxial re-growth process in combination with the Smart Cut™ technology. An original process integration scheme is described in order to minimize the diode leakage.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125130075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
On the optimization of SiGe and III-V compound hetero-junction Tunnel FET devices SiGe和III-V复合异质结隧道场效应管器件的优化研究
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818816
A. Revelant, P. Palestri, P. Osgnach, D. Lizzit, L. Selmi
{"title":"On the optimization of SiGe and III-V compound hetero-junction Tunnel FET devices","authors":"A. Revelant, P. Palestri, P. Osgnach, D. Lizzit, L. Selmi","doi":"10.1109/ESSDERC.2013.6818816","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818816","url":null,"abstract":"We investigate the operation and performance of planar SiGe/Si and In<sub>0.53</sub>Ga<sub>0.47</sub>As/In<sub>0.7</sub>Ga<sub>0.3</sub>As/In<sub>0.53</sub>Ga<sub>0.47</sub>As hetero-junction Semiconductor on Insulator (ScOI) Tunnel FET (TFET) devices. The alignment between the hetero-junction, the gate edge and the source junction is systematically shifted to search for the highest ON-current and the lowest Subthreshold Swing (SS). A slight positive misalignment between the hetero-junction and the metallurgical junction is beneficial to improve I<sub>ON</sub> but for the considered devices the ON-current at V<sub>DD</sub>=0.5V and I<sub>oFF</sub>=1pA/μm hardly exceeds 1μA/μm. Furthers reduction of the band gap by lattice strain appears mandatory to exceed this limit in the explored material systems.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127418948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Modeling and characterization of hot-carrier stress degradation in power MOSFETs (invited) 功率mosfet中热载流子应力退化的建模和表征(特邀)
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818826
S. Reggiani, E. Gnani, A. Gnudi, G. Baccarani, S. Poli, R. Wise, M.-Y Chuang, W. Tian, M. Denison
{"title":"Modeling and characterization of hot-carrier stress degradation in power MOSFETs (invited)","authors":"S. Reggiani, E. Gnani, A. Gnudi, G. Baccarani, S. Poli, R. Wise, M.-Y Chuang, W. Tian, M. Denison","doi":"10.1109/ESSDERC.2013.6818826","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818826","url":null,"abstract":"Power device reliability is one of the key challenges of next generation Smart-Power technologies. As a consequence, device performance needs to be optimized accounting for hot-carrier stress degradation issues. To this purpose, numerical simulation tools are commonly used, but the TCAD modeling of performance drifts due to electrical stress is still an open issue. Physics-based analytical models and TCAD based approaches have been proposed and devised for the investigation of the parameter degradation in the linear transport regime and its localization in STI-based LDMOS devices. A thorough investigation of the degradation under high-gate stress biases, corresponding to impact-ionization regimes, is carried out to gain an insight on the overall bias and temperature dependence of the parameter drifts.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126092364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Gate stack optimization to minimize power consumption in super-lattice fets 栅极堆栈优化以最小化超晶格场效应管的功耗
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818824
P. Maiorano, E. Gnani, A. Gnudi, S. Reggiani, G. Baccarani
{"title":"Gate stack optimization to minimize power consumption in super-lattice fets","authors":"P. Maiorano, E. Gnani, A. Gnudi, S. Reggiani, G. Baccarani","doi":"10.1109/ESSDERC.2013.6818824","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818824","url":null,"abstract":"In this work the effect of high-k gate dielectrics on the power-speed performance of SL-FETs realized with the InGaAs/InAlAs and InGaAs/InP material pairs is investigated by numerical simulations. The analysis shows that the InGaAs/InP pair, in association with Al2O3 as the gate dielectric, provides the most promising results for high-performance applications, i.e. an on-state current approaching 2 mA/μm and an intrinsic delay lower than 0.16 ps at a supply voltage of 0.4 V. The average subthreshold swing SS is much lower than 60 mV/dec over six current decades and the point slope SS ≈ 20mV/dec. These results outperform the ITRS requirements projected to year 2022 in terms of both static and dynamic power dissipation, and make the proposed device well suited for high-performance and low-power applications at the same time.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128566527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Mobility enhancement by integration of TmSiO IL in 0.65nm EOT high-k/metal gate MOSFETs 在0.65nm EOT高k/金属栅mosfet中集成TmSiO IL增强迁移率
2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818842
E. Litta, P. Hellström, M. Östling
{"title":"Mobility enhancement by integration of TmSiO IL in 0.65nm EOT high-k/metal gate MOSFETs","authors":"E. Litta, P. Hellström, M. Östling","doi":"10.1109/ESSDERC.2013.6818842","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818842","url":null,"abstract":"Thulium silicate has been demonstrated as a possible replacement of chemical oxide interfacial layers for extended scalability of high-k/metal gate MOSFETs. In this work, thulium silicate was integrated in a scaled HfO2/TiN gate-last CMOS process, achieving an EOT of 0.65 nm and well-behaved and reproducible IV and CV characteristics with almost symmetric threshold voltages, low subthreshold slope and low hysteresis. Comparison with reference devices employing chemical oxide interfacial layers shows improvement in terms of leakage current density and electron and hole mobility. Specifically, channel mobility is enhanced by 20% in N-MOSFETs and by 15% in P-MOSFETs at an inversion charge density of 1013cm-2, yielding values of 180 and 75 cm2/Vs at EOT = 0.65 and 0.8 nm respectively.","PeriodicalId":112804,"journal":{"name":"2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128430897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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