2023 IEEE Custom Integrated Circuits Conference (CICC)最新文献_第3页

2023 IEEE Custom Integrated Circuits Conference (CICC) Committees 2023 IEEE自定义集成电路会议(CICC)委员会

2023 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2023-04-01 DOI: 10.1109/cicc57935.2023.10121212

引用次数: 0

A 25.0-to-35.9GHz Dual-Layer Quad-Core Dual-Mode VCO with 189.1dBc/Hz FoM and 200.2dBc/Hz FoMT at 1MHz Offset in 65nm CMOS 一个25.0至35.9 ghz的双层四核双模VCO，具有189.1dBc/Hz的FoM和200.2dBc/Hz的FoM，在65nm CMOS的1MHz偏移

2023 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2023-04-01 DOI: 10.1109/CICC57935.2023.10121234

Pingda Guan, Haikun Jia, W. Deng, Ruichang Ma, Huabing Liao, Zhihua Wang, B. Chi

{"title":"A 25.0-to-35.9GHz Dual-Layer Quad-Core Dual-Mode VCO with 189.1dBc/Hz FoM and 200.2dBc/Hz FoMT at 1MHz Offset in 65nm CMOS","authors":"Pingda Guan, Haikun Jia, W. Deng, Ruichang Ma, Huabing Liao, Zhihua Wang, B. Chi","doi":"10.1109/CICC57935.2023.10121234","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121234","url":null,"abstract":"The 5 G communication has placed stringent requirements on the performance of local oscillators (LOs). The LO needs a wide frequency tuning range to cover the various mm-wave frequency bands allocated for 5 G communication and ultra-low phase noise to support advanced modulations such as 1024-QAM. However, with increasing parasitic effects and limited quality factors of passive components in mm-wave bands, it is challenging to meet such requirements. For low phase noise, multi-core technologies have been widely used [1 –5]. Coupled N cores optimize the phase noise by $10 log (N) d B$. For a wide tuning range, multi-mode technologies have been developed [1 –3]. Multiple oscillation modes extend the frequency tuning range with less phase noise penalty than simply enlarging capacitor banks or varactors. Another critical but rarely discussed aspect of oscillators is the supply voltage VDD. A standard VDD is imperative for the system integration of oscillators. However, VDD lower than the standard is used in many reported oscillators to optimize the FoM [1–2]. When a standard VDD is applied to those oscillators, low-dropout regulators (LDOs) or tail current sources are necessary to control the voltage swing. Otherwise, the oscillator core would face reliability issues. The LDOs or tail current sources consume extra power, inevitably degrading the overall FoM.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132164975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 138-TOPS/W Delta-Sigma Modulator-Based Variable- Resolution Activation in-Memory Computing Macro 一个基于138-TOPS/W Delta-Sigma调制器的可变分辨率激活内存计算宏

2023 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2023-04-01 DOI: 10.1109/CICC57935.2023.10121312

Vasundhara Damodaran, Ziyu Liu, Jae-sun Seo, A. Sanyal

{"title":"A 138-TOPS/W Delta-Sigma Modulator-Based Variable- Resolution Activation in-Memory Computing Macro","authors":"Vasundhara Damodaran, Ziyu Liu, Jae-sun Seo, A. Sanyal","doi":"10.1109/CICC57935.2023.10121312","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121312","url":null,"abstract":"In-memory computing (1MC) is a widely used technique that performs low-precision computations inside memory elements to break the von-Neumann bottleneck in conventional A1/ML hardware. Recently SRAM based 1MC [1–4] has gained significant attention due to its high energy efficiency and easy integration with CMOS 1Cs. A fundamental limitation of SRAM based 1MC is nonlinearity in the multiply-and-accumulate (MAC) operation. For large values of MAC result, the proportional large discharge current through SRAM bitline pushes the access transistors into linear region and makes the discharge current, and hence the MAC result, a nonlinear function of bitline voltage [1–3]. Recent works have tried to address this fundamental limitation by applying pulsed input activations [3] and adding capacitors to SRAM bitcell [4–5] for charge-domain computation which has much lower sensitivity to bitline voltage, and hence, higher linearity than current-domain computation in traditional SRAM bitcell. While pulsed input makes each SRAM bitcell linear, accumulation of paitial products is still performed in current-domain and the overall MAC result is still nonlinear [3]. The capacitive SRAM in [4–5] improves linearity over current-domain accumulation by making the MAC result independent of the discharge current. However, linearity of MAC is still limited since the analog input is sampled on the capacitor in the bitcell through an NMOS switch. The analog input activation modulates threshold voltage (Vth) of the NMOS switch making the voltage sampled on the capacitor nonlinear. Vth drop in the NMOS capacitor also limits the maximum input swing that can be handled by the SRAM bitcell and restricts the supply voltage to relatively high values.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132331848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A 38GHz Power-Combined Doherty PA Based on an Extended Rat-Race Coupler Achieving 27.5dBm Saturated Power and 15.0% Efficiency at 6dB Back-Off 基于扩展鼠型耦合器的38GHz功率组合Doherty PA在6dB回退时实现27.5dBm饱和功率和15.0%效率

2023 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2023-04-01 DOI: 10.1109/CICC57935.2023.10121179

Xiaohan Zhang, Sensen Li, T. Chi

{"title":"A 38GHz Power-Combined Doherty PA Based on an Extended Rat-Race Coupler Achieving 27.5dBm Saturated Power and 15.0% Efficiency at 6dB Back-Off","authors":"Xiaohan Zhang, Sensen Li, T. Chi","doi":"10.1109/CICC57935.2023.10121179","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121179","url":null,"abstract":"Phased arrays serve as the foundational technology for mmWave communications to combat the path loss and improve the energy efficiency. Although phased arrays are ubiquitous at mmWave, it is still desirable to realize high output power per antenna for user equipment (UE) and small cells due to their array size constraints. Recent advances in mmWave silicon power amplifier (PA) research have led to significant performance improvement for low-and medium-power PAs $(lt 23 mathrm{dBm})$. However, design of high-power yet high-efficiency PAs still remains challenging.This work aims to demonstrate Watt-level PA output power $(gt 27 mathrm{dBm})$ with back-off efficiency enhancement. Back-off efficiency enhancement is particularly attractive for UE and small-cell PAs to extend their battery lives under spectral-efficient modulations. Among various efficiency enhancement techniques, Doherty architecture can potentially enable wider bandwidths due to its lower digital computation overhead. Therefore, our design goal is to develop a multi-functional PA output network to achieve (1) Doherty load modulation, (2) multi-way power combining, and (3) differential to single-ended conversion simultaneously, as shown in Fig. 1.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123363447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

DenseCIM: Binary Weighted-Capacitor SRAM Computation-In-Memory with Column-by-Column Dynamic Range Calibration SAR ADC DenseCIM:具有逐列动态范围校准SAR ADC的二进制加权电容SRAM内存计算

2023 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2023-04-01 DOI: 10.1109/CICC57935.2023.10121213

Yong-Jun Jo, Boon Peng Yap, Dong-Hyun Yoon, Hyunjoon Kim, Yuanjin Zheng, T. T. Kim

{"title":"DenseCIM: Binary Weighted-Capacitor SRAM Computation-In-Memory with Column-by-Column Dynamic Range Calibration SAR ADC","authors":"Yong-Jun Jo, Boon Peng Yap, Dong-Hyun Yoon, Hyunjoon Kim, Yuanjin Zheng, T. T. Kim","doi":"10.1109/CICC57935.2023.10121213","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121213","url":null,"abstract":"As computation-in-memory (C1M) architecture is a prominent solution for energy efficiency in Al edge devices, designing a robust, accurate, and dense C1M architecture has become essential. Capacitor-based C1M has been widely adopted thanks to the high linearity of the capacitors. Fig. 1 explains various challenges and motivations of C1M with the proposed C1M architecture. The first challenge is to implement linear multi-bit computing. A multiply-and accumulation (MAC) value with different input and weight combinations shows different analog MAC voltages, degrading accuracy. Bit-parallel is an alternate solution for realizing multi-bit computing [1]. However, it shows significant power and area overheads because of multiple analog-to-digital converters (ADCs) and shift-and-adders for one MAC operation. Another challenge is ADC dynamic range utilization. Because the analog MAC dynamic range depends on neural-network, it is smaller than ADC dynamic range. This dynamic range mismatch degenerates the resolution with the same ADC bit-width. The last challenge is the area overhead of the ADC, which requires the ADC to be shared. The ADC shared with N columns degrades throughput by 1/N and requires Opamps to keep the analog MAC voltages from non-selected columns. To address the above issues, this paper proposes: (i) Capacitive coupling-based weighted-capacitor SRAM C1M (WC-CIM) with linear multi-bit computing, (ii) ADC dynamic range calibration (DRC) to improve resolution and minimize wasted dynamic range, and (iii) A novel capacitive-DAC (cap-DAC) driver with shared successive approximation (SAR) logic [2] for compact ADC.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121744666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Li-ion Battery Input 96.8% Peak Efficiency Single- Inductor Off-Chip-Capacitor-Free 2-Switch LED Driver with Two-Color Mixing Capability 锂离子电池输入96.8%的峰值效率，单电感片外无电容2开关LED驱动器与双色混合能力

2023 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2023-04-01 DOI: 10.1109/CICC57935.2023.10121297

Caiyu Tong, Zihao Fan, Yuan Gao

{"title":"A Li-ion Battery Input 96.8% Peak Efficiency Single- Inductor Off-Chip-Capacitor-Free 2-Switch LED Driver with Two-Color Mixing Capability","authors":"Caiyu Tong, Zihao Fan, Yuan Gao","doi":"10.1109/CICC57935.2023.10121297","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121297","url":null,"abstract":"Li-ion battery-powered LED illumination provides a wide range of potential applications for portable devices. It is always desirable to design an LED driver that uses the fewest off-chip components, operates with higher efficiency, and includes extra features such as color mixing. As shown in Fig. 1, the buck-boost topology is commonly adopted as the battery voltage (from $2.7 mathrm{~V}$ to $4.2 mathrm{~V}$) can be either higher or lower than the forward voltage of LED. However, its power stage consists of four switches, each of which suffers from switching and conduction losses. In addition, it is not $P C B$ area efficient to include at least three off-chip components (an inductor and input and output capacitors) [1–2]. The recent introduction of various hybrid buck-boost converters helps to improve efficiency by reducing effective resistance that the main current flow through, but at the expense of the extra off-chip flying capacitors [3–5]. Moreover, to drive LEDs for color mixing, these general-purpose converters need to pay additional power to regulate and balance the current, especially when the forward voltages of LEDs are unequal [6].","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127677746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Fully-Dynamic kT/C-Noise-Canceled SAR ADC with Trimming-Free Dynamic Amplifier 带无调边动态放大器的全动态kT/ c消噪SAR ADC

2023 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2023-04-01 DOI: 10.1109/CICC57935.2023.10121326

Haoyu Zhuang, Nan Sun, Li Tao, Yizhan Li, Oiang Li

{"title":"A Fully-Dynamic kT/C-Noise-Canceled SAR ADC with Trimming-Free Dynamic Amplifier","authors":"Haoyu Zhuang, Nan Sun, Li Tao, Yizhan Li, Oiang Li","doi":"10.1109/CICC57935.2023.10121326","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121326","url":null,"abstract":"Nowadays, SAR ADC is popular due to the high energy efficiency. However, in high-resolution applications, the power and area are too large as the kT/C-noise requirement leads to a huge capacitive DAC. To solve this issue, several techniques to cancel the kT/C noise have been reported in [1] –[3]. Among them, [1]–[2] use an amplifier with static current to cancel the kT/C noise. Despite its effectiveness, it wastes much energy in low-duty-cycle circumstances (low sampling rate), since the static amplifier is always active even when the ADC works in the tracking mode. This static amplifier cannot be disabled to save power, since the static amplifier wakes up slowly and it is unknown when the next sampling instance will come, i.e., in event driven applications. Also, in some commercial ADC products, such as AD7982 [4], it is a significant consideration to have no static current in the tracking mode, and their fully-dynamic operation is highlighted as an important feature. To realize dynamic operation, [3] proposes a fully-dynamic kT/C-noise cancellation in a noise-shaping SAR. Nevertheless, it requires an accurate gain of dynamic amplifier to cancel the kT/C noise. This leads to an extra trimming during test, which increases the cost severely for commercial products.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133310688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A 52-67GHz Ultra-Compact Bi-directional Gate-switching Cascode Amplifier with Tri-coil Broadband Matching in 40-nm CMOS 一种40纳米CMOS三圈宽带匹配的52-67GHz超紧凑双向门开关级联放大器

2023 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2023-04-01 DOI: 10.1109/CICC57935.2023.10121214

Haoyang Jia, Yanjie Wang, A. Zhu

引用次数: 0

A 3D-integrated 8λ × 32 Gbps λ Silicon Photonic Microring-based DWDM Transmitter 一种3d集成的8λ × 32gbps λ硅光子微通DWDM发射机

2023 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2023-04-01 DOI: 10.1109/CICC57935.2023.10121265

Cooper S. Levy, Z. Xuan, Duanni Huang, Ranjeet Kumar, J. Sharma, Taehwan Kim, Chaoxuan Ma, G. Su, Songtao Liu, Jinyong Kim, Xinru Wu, G. Balamurugan, H. Rong, J. Jaussi

{"title":"A 3D-integrated 8λ × 32 Gbps λ Silicon Photonic Microring-based DWDM Transmitter","authors":"Cooper S. Levy, Z. Xuan, Duanni Huang, Ranjeet Kumar, J. Sharma, Taehwan Kim, Chaoxuan Ma, G. Su, Songtao Liu, Jinyong Kim, Xinru Wu, G. Balamurugan, H. Rong, J. Jaussi","doi":"10.1109/CICC57935.2023.10121265","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121265","url":null,"abstract":"Silicon photonics-based optical 1/O is a promising technology direction to meet the ever growing off-chip 1/O bandwidth needs of data-intensive computing. While silicon photonic (SiPh) transceivers are increasingly being used in pluggable modules for data center communications, the power efficiency and latency constraints for their integration in XPU/switch packages (such as recent demonstrations in [1], [2]) are significantly more stringent, requiring different solutions. Ring resonator-based transceiver architectures are attractive for this application due to their small footprint and suitability for dense wavelength division multiplexing (DWDM), which enables energy-efficient bandwidth scaling. System demonstrations of ring-based transceivers with per-wavelength data rates of up to 16 Gb/s and low BER (<1e-12) have been shown recently [2]; however, these require an external multi-wavelength laser source, increasing optical path loss and requiring additional fibers be attached to the compute package. Prior demonstrations have shown higher baud rates in ring-based systems, but modulate only one wavelength at a time [3], [4]. This paper presents a SiPh microring-based TX that includes all photonic and electronic components needed to support simultaneous modulation of eight 200 GHz-spaced wavelengths at 32 Gbps/λ (for an aggregate bandwidth of 256 Gbps/fiber).","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"249 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131585200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

An 86.5-105.6GHz LO Generator with Cascaded Implicit Frequency Quintupling and Tripling Achieving -107.7 dBc/Hz Phase Noise and 191. 2dBc/Hz FoM at 1MHz Offset 具有级联隐式五倍频和三倍频的86.5-105.6GHz本振发生器实现-107.7 dBc/Hz相位噪声和191。2dBc/Hz FoM在1MHz偏移

2023 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2023-04-01 DOI: 10.1109/CICC57935.2023.10121289

Hao Guo, T. Chi

引用次数: 0