An 86.5-105.6GHz LO Generator with Cascaded Implicit Frequency Quintupling and Tripling Achieving -107.7 dBc/Hz Phase Noise and 191. 2dBc/Hz FoM at 1MHz Offset
{"title":"An 86.5-105.6GHz LO Generator with Cascaded Implicit Frequency Quintupling and Tripling Achieving -107.7 dBc/Hz Phase Noise and 191. 2dBc/Hz FoM at 1MHz Offset","authors":"Hao Guo, T. Chi","doi":"10.1109/CICC57935.2023.10121289","DOIUrl":null,"url":null,"abstract":"100+GHz frequency bands offer great potential for next-generation wireless communications and sensing. A major technical challenge for 100+GHz transceivers is the design of high-purity yet low-power local oscillators (LO) – the reported FoM at lMHz offset has been limited to < 180dBc/Hz. Fundamental VCOs at such high frequencies have poor FoM and phase noise (PN) due to the low quality factor (O) of capacitor banks. Alternatively, implicit or explicit frequency multipliers can be used to extract harmonics from a fundamental VCO running at lower frequencies. However, the mainstream frequency multiplier topologies have a limited multiplication factor (× 3or× 4) [1, 2], meaning that to generate the desired 100GHz output, the fundamental VCOs need to work at 25-33GHz with $\\sim$190dBc/HzFoM to start with. Counting in the additional DC power of the harmonic extraction circuit and output buffer, the best achievable FoM at $\\sim$100GHz still cannot exceed 190dBc/Hz.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE Custom Integrated Circuits Conference (CICC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC57935.2023.10121289","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
100+GHz frequency bands offer great potential for next-generation wireless communications and sensing. A major technical challenge for 100+GHz transceivers is the design of high-purity yet low-power local oscillators (LO) – the reported FoM at lMHz offset has been limited to < 180dBc/Hz. Fundamental VCOs at such high frequencies have poor FoM and phase noise (PN) due to the low quality factor (O) of capacitor banks. Alternatively, implicit or explicit frequency multipliers can be used to extract harmonics from a fundamental VCO running at lower frequencies. However, the mainstream frequency multiplier topologies have a limited multiplication factor (× 3or× 4) [1, 2], meaning that to generate the desired 100GHz output, the fundamental VCOs need to work at 25-33GHz with $\sim$190dBc/HzFoM to start with. Counting in the additional DC power of the harmonic extraction circuit and output buffer, the best achievable FoM at $\sim$100GHz still cannot exceed 190dBc/Hz.