An 86.5-105.6GHz LO Generator with Cascaded Implicit Frequency Quintupling and Tripling Achieving -107.7 dBc/Hz Phase Noise and 191. 2dBc/Hz FoM at 1MHz Offset

Hao Guo, T. Chi
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Abstract

100+GHz frequency bands offer great potential for next-generation wireless communications and sensing. A major technical challenge for 100+GHz transceivers is the design of high-purity yet low-power local oscillators (LO) – the reported FoM at lMHz offset has been limited to < 180dBc/Hz. Fundamental VCOs at such high frequencies have poor FoM and phase noise (PN) due to the low quality factor (O) of capacitor banks. Alternatively, implicit or explicit frequency multipliers can be used to extract harmonics from a fundamental VCO running at lower frequencies. However, the mainstream frequency multiplier topologies have a limited multiplication factor (× 3or× 4) [1, 2], meaning that to generate the desired 100GHz output, the fundamental VCOs need to work at 25-33GHz with $\sim$190dBc/HzFoM to start with. Counting in the additional DC power of the harmonic extraction circuit and output buffer, the best achievable FoM at $\sim$100GHz still cannot exceed 190dBc/Hz.
具有级联隐式五倍频和三倍频的86.5-105.6GHz本振发生器实现-107.7 dBc/Hz相位噪声和191。2dBc/Hz FoM在1MHz偏移
100+GHz频段为下一代无线通信和传感提供了巨大的潜力。100+GHz收发器的一个主要技术挑战是高纯度低功耗本振(LO)的设计——据报道,lMHz偏置时的FoM被限制在< 180dBc/Hz。在如此高的频率下,由于电容器组的低质量因数(O),基频压控振荡器具有较差的FoM和相位噪声(PN)。另外,隐式或显式乘频器可用于从运行在较低频率的基频压控振荡器中提取谐波。然而,主流倍频器拓扑具有有限的倍增因子(× 3or× 4)[1,2],这意味着要产生所需的100GHz输出,基本vco需要在25-33GHz工作,$\sim$190dBc/HzFoM开始。算上谐波提取电路和输出缓冲器的额外直流功率,在100GHz下可实现的最佳FoM仍不超过190dBc/Hz。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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