2023 IEEE Custom Integrated Circuits Conference (CICC)最新文献

{"title":"A Monolithic 3D Magnetic Sensor in 65nm CMOS with <10μTrms Noise and 14.8μW Power","authors":"Saransh Sharma, Hayward Melton, Liliana Edmonds, O. Addington, Mikhail G. Shapiro, A. Emami-Neyestanak","doi":"10.1109/CICC57935.2023.10121313","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121313","url":null,"abstract":"Magnetic sensors have become increasingly ubiquitous as they constitute an integral part of several fast-growing sectors such as automotive, navigation, robotics, medical devices and consumer electronics [1] –[6]. Due to their compatibility with the standard CMOS process, Hall magnetic sensors are widely used. However, one of the key challenges of CMOS-based Hall sensors is their relatively low sensitivity, which is inevitable given the low Hall coefficient of Si. For better sensitivity, Hall sensors are biased at higher current levels which hinders their widescale use in low-power bioelectronics and other power-constrained applications. Another challenge is the difficulty in implementing high-sensitivity vertical Hall elements in planar CMOS processes for 3D sensing. This is often overcome by using ferromagnetic materials that require additional and expensive steps during fabrication, thus increasing the cost [2] [3].","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116892968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An ELDC-Free 2.78mW 20MHz-BW 75.5dB-SNDR 4th- Order CTSDM Facilitated by 2nd-Order CT NS-SAR and AC-Coupled Negative-R","authors":"ZiXuan Xu, Kai Xing, Yan Zhu, Chi-Hang Chan, R. Martins","doi":"10.1109/CICC57935.2023.10121316","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121316","url":null,"abstract":"Continuous-time (CT) SDMs inherent anti-aliasing and the relatively high and constant input impedance feature, easing the ADC driver design when compared with its discrete-time (DT) counterparts. While in a hybrid structure with a DT noise-shaping SAR (NS-SAR) quantizer (OTZ), the efficiency of CTSDMs can further improve [3] [4]. However, the necessitation of the excess loop delay (ELD) compensation (ELDC) in CTSDMs poses additional power overhead. Especially, the NS-SAR OTZ performs multiple bit quantization and integration in series, requires a substantial delay ($mathrm{t}_{mathrm{d}}$) compensation, leading to a power-hungry loop filter. Poor compensations in highorder designs also deteriorate the in-band noise floor and even cause loop instability. As depicted in Fig.1, the compensation generally is accomplished with a fast feedback path from the OTZ’s output to input, which can be done in a number of ways [1] [2] [3] [4]. Conventional ELDC exploits an additional summing amplifier with a direct feedback ELD DAC [1], thus being energy inefficient. in [2] [3], ELDC is embedded into the integrator, saving the feedback DAC and the amplifier; but simultaneously demanding power-hungry lntegrators with higher specifications. The implementation of the ELDC can happen inside the DAC of the SAR OTZ [4]; however, this implies an additional operation phase and undesired load for the integrator. This paper proposes an ELDC-free CTSDM facilitated by a CT-NS SAR OTZ. incorporating a single amplifier biquad (SAB) and an AC+DC negative-R technique, the prototype reaches 75. 5dB SNDR with 20MHz bandwidth (BW) and 2. 78mW power, yielding a Walden Figure-of-merit (Fo$mathrm{M}_{mathrm{W}}$) and a Schreier FoM (FOMs) of 14.3 fJ/conversion-step and 174.1dB, respectively.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121250528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 0.06-mm2 Current-Mode Noise-Shaping SAR based Temperature-to-Digital Converter with a 4.9-nJ Energy/Conversion","authors":"A. Aprile, Michele Folz, D. Gardino, P. Malcovati, E. Bonizzoni","doi":"10.1109/CICC57935.2023.10121267","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121267","url":null,"abstract":"MEMS accelerometers and gyroscopes employed in state-of-the-art battery-supplied motion sensing systems require ultra-low energyper-conversion (<10nJ) digital temperature data to compensate for the thermal drift of their sensed quantities. Furthermore, in order to meet the increasingly stringent demands of the market, the cost-effectiveness of these devices should be ensured by compact temperature compensation solutions (<0.1 mm2), referred to as Temperature-to-Digital Converters (TDCs). Taking the moderate accuracy requirements (<2%) for the considered application into account, BJT-based sensors are a good option for the analog part of the TDC, since their low-cost 1 -pt calibration is sufficient [1] –[3]; moreover, considering that also the resolution requirements are moderate (<200mK), with the goal of minimizing the TDC conversion energy, a SAR-based architecture to perform the analog-to-digital conversion is undoubtedly the best approach [4] –[6]. In this paper we introduce a Noise Shaping (NS) SAR based TDC with a resolution refining process exploiting an error-feedback approach; the sensor, equipped with an NPN-based bipolar core, has been completely designed in the current domain, feature that allows opamp-less signal processing. A block diagram of the proposed NSSAR based TDC is shown in Fig. 1. The BJT Core is composed by proportional and complementary to-absolute-temperature (PTAT and CTAT) current sources, which generate the signals needed for the temperature-to-digital conversion ($mathrm{I}_{mathrm{P}mathrm{T}mathrm{A}mathrm{T}}$, IREF* and IREF = IPTATI + ICTATI) [4]. These signals are delivered to the Current-Mode NS-SAR by means of three interface circuits, an n-type current mirror and two current buffers. IPTAT contains the temperature information to be converted while IREF**, a replica of IREF*, is provided as a reference signal to a binary p-type 4-bit current steering DAC, which scales it sequentially according to a successive approximation algorithm (IDAC =$mathfrak{a}_{mathrm{D}mathrm{A}}$c.$1_{mathrm{R}mathrm{E}mathrm{F}^{starstar}}$); IREF, instead, is used to set the proper conversion range upshifting $1_{mathrm{D}mathrm{A}mathrm{C}}$ to obtain ISAR =$1_{mathrm{R}mathrm{E}mathrm{F}}$+ IDAC. Each 4-bit conversion is carried out in 4 clock cycles, in which the subsequent decisions of a current comparator about the polarity of the ADC input signals (1X and ISAR) are processed by the SAR logic; then, in a dedicated clock period, a noise shaper generates a residue current (IRES) that is fed-back to the ADC input and added to IPTAT to form $1_{mathrm{X}}$=$1_{mathrm{P}mathrm{T}mathrm{A}mathrm{T}+}$ IRES. The 4-bit codestream obtained by a cyclic operation of the described conversion process is finally delivered to a decimation filter which, for testing flexibility reasons, has been kept off-chip. Depending on the selected oversampling-ratio (OSR), it generates more refined digital codes with a I/(OSR.$mathrm{T}_{mathrm{s}}$) r","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"2605 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127484216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CIMC: A 603TOPS/W In-Memory-Computing C3T Macro with Boolean/Convolutional Operation for Cryogenic Computing","authors":"Yuhao Shu, Hongtu Zhang, Qi Deng, Hao Sun, Y. Ha","doi":"10.1109/CICC57935.2023.10121295","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121295","url":null,"abstract":"Cryogenic computing is a promising solution to pursue higher energy efficiency of circuits due to its significantly reduced device leakage and wire resistance. However, existing IMC macros [1–5] still have several challenges in improving energy efficiency at cryogenic temperature: (1) Existing cryogenic eDRAMs are not optimal for achieving reliable write operations. (2) Cryogenic computing requires cryogenic IMC based Boolean functions and (3) energy-efficient convolution operation. We present energy-efficient cryogenic computing. To address these challenges, we present a cryogenic IMC macro (CIMC) employing three effective techniques: (1) A reliable cryogenic 3T (C3T) bitcell that realizes full-swing data transmission with high data retention time. (2) An accurate implementation of cryogenic Boolean functions with adaptive- reference sense amplifiers (ARSAs) (3) Fast and low power cryogenic convolutions with optimized Flash ADC. Measurement results show our work has achieved an average energy efficiency of 603.1TOPS$/mathrm{W}(4mathrm{b} times4mathrm{b})$ and an average computing density of 284TOPS/mm $^{2},(4 mathrm{b}times4mathrm{b})$.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124911804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"2023 Program-at-a-Glance","authors":"","doi":"10.1109/cicc57935.2023.10121279","DOIUrl":"https://doi.org/10.1109/cicc57935.2023.10121279","url":null,"abstract":"","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114591802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cryogenic CMOS: design considerations for future quantum computing systems","authors":"R. Joshi, J. Plouchart, G. Zettles, Scott Willenborg, S. Chakraborty, B. Johnson, Andrew P. Wack, B. Allison, John Timmerwilke, K. Tien, M. Yeck, Dereje Yilma, A. Valdes-Garcia, D. Friedman","doi":"10.1109/CICC57935.2023.10121274","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121274","url":null,"abstract":"Today’s quantum computing systems rely on commercial electronics operating at room temperature in order to perform control and readout operations for qubits [1] –[6]. The qubits operate at cryogenic temperatures; the signals that support control and readout of qubits therefore traverse multiple temperature stages in a dilution refrigerator to enable interaction with the qubits of a quantum computer. For many of the most advanced quantum computers built to date, the control of each individual qubit demands application of a radiofrequency pulse that is precisely calibrated in frequency, amplitude, and phase. Oubit readout demands the amplification of very low amplitude signals that are then post-processed to categorize the state of the qubit being measured. Oubit control electronics are implemented using arbitrary waveform generators (AWGs) of various types. The scalability of such systems is challenged by the need to scale the number of qubit control electronics units linearly with the number of qubits in the system. One approach to mitigating this challenge that is under active exploration is the use of multi-channel AWGs (tailored to the requirements of qubit control) that operate at the 4K stage of a quantum computing system [7] –[10]. Oubit readout electronics are typically implemented using multiple stages of amplification and then DSP-based readout performed at room temperature. In today’s systems, while readout electronics benefits from multiplexing of the readout signals (enabling a single cascade of moderately wideband amplifiers to support the delivery of multiple readout signals to the room-temperature electronics), again, the scalability of this approach is challenged much as is the case with control electronics. One approach to mitigating the readout challenge is the expanded use of cryogenic electronics in the readout chain. Success in the implementation of cryogenic control and readout solutions depends critically on multiple CMOS sub-components; in this paper we focus on SRAM and low noise amplifiers (LNAs). Note that SRAM is critical for both control and readout applications as a mixed-signal solution involving the combination of a custom processor and analog elements is highly desirable in both cases. Further, while the LNA is directly used as an element in the readout chain, a deep assessment of LNA performance and opportunities strongly benefits overall understanding of achievable noise performance in CMOS technologies at cryogenic temperatures and is therefore impoitant in both control and readout contexts.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130389050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Wireless Implantable Opto-Electro Neural Interface ASIC for Simultaneous Neural Recording and Stimulation","authors":"Linran Zhao, Yan Gong, Wei Shi, R. Stephany, Wen Li, Y. Jia","doi":"10.1109/CICC57935.2023.10121181","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121181","url":null,"abstract":"Recent advances in optogenetics enable optical stimulation that uses light to reversibly control the activity of the genetically targeted specific neurons. Optical stimulation has distinct advantages of cell specificity, high temporal precision, and rapid reversibility, compared to electrical stimulation [1] –[4]. LEDs typically require high instantaneous current in the order of mA level to emit sufficient light for effective optical stimulation. Such a power-consuming function will challenge wireless power transmission. Wireless operation in terms of power delivery and data transmission is highly desired for eliminating tethers, batteries, and limitations during in vivo studies. Thus, energy-efficiency optical stimulation circuits are required. In addition, the stimulation-induced artifacts can corrupt neural recording and lead to saturation of sensing frontend (SFE) circuits. Neural interface ASIC for simultaneous neural recording and stimulation requires an SFE that can tolerate large artifacts. Hence, we present a novel wireless implantable opto-electro (WIOE) neural interface ASIC with features of artifact-tolerant SFE, energy-efficient optical stimulation, and wireless and battery-free operation.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127032107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 28nm All-Digital, 1.92-7.32mV/LSB, 0.5-2GS/s sample rate, 0-latency Voltage Sensor with Dynamic PVT Calibration for Wide-range Adaptive Voltage Scaling","authors":"Yuxuan Du, Haitao Ge, Zhuo Chen, Kaize Zhou, Zheng-Kun Shen, Weiwei Shan","doi":"10.1109/CICC57935.2023.10121271","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121271","url":null,"abstract":"On-chip supply-voltage droops induced by work-load variations are severe in processors that the $1^{text {st}}$ droop may cause up to 137 mV voltage reduction during 10 ns [5] (Figure. 1 top left). All-digital fully integrated voltage sensors are favored over analog comparators [1] for SoCs for their higher speed and resolution, either based on digital CMOS delay lines [2, 3, 4] or ring oscillators [5]. High-speed voltage sensors for droop detection face three challenges: (1) The sampling counter of the ring oscillator caused several cycles of latency and load imbalance thus increasing output jitter. (2) The process, temperature and linearity of voltage (PVT) variation cause oscillation times per cycle to vary, requiring large calibration costs. (3) The detected voltage sensor output always endures several cycles of latency from real droop occurrence, leading to delayed response.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130573762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"dToF LIDAR System Using Addressable Multi-Channel VCSEL Transmitter, 128x80 SPAD Sensor, and ML-Based Object Detection for Adaptive Beam-Steering","authors":"Yifan Wu, Sifan Zhou, Miao Sun, Tao Xia, Jian Qian, Lei Wang, Shi-min Shi, Lebei Cui, Chill Wang, Yuan Li, Hengwei Yu, Zhihong Lin, Lei Qiu, Yajie Qin, Min Sun, Rui Bai, Xuefeng Chen, Patrick Chiang, Shenglong Zhuo","doi":"10.1109/CICC57935.2023.10121184","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121184","url":null,"abstract":"Light detection and ranging (LiDAR) technology is increasingly being deployed in vehicles for advanced driving assistance system (ADAS) and is a potential critical technology for autonomous driving in the future. Currently, hybrid solid-state LiDARs based on micro-electro- mechanical system (MEMS) or rotating mirrors are the most mature solutions [1]. Unfortunately, these hybrid LiDARs still exhibit high risk of damage due to their limited mechanical reliability in harsh environments across many years of operation. Furthermore, these solutions require highly accurate calibration due to the complex optical alignment, resulting in higher production cost. Compared with these mechanical solutions, solid-state flash LiDARs without any moving parts are easier to mass-produce, more robust, less costly, and exhibit smaller form-factor, allowing flash-LiDAR to be embedded in multiple places around the automobile. Nevertheless, the detection distance of a single-flash LiDAR is short due to the smaller optical power limited by the laser eye-safety requirement, VCSEL thermal heating, and long-term VCSEL reliability [2]. Furthermore, for some applications, the distance of only one or two nearest objects needs to be accurately measured, and therefore empty parts of the field-of-view (FOV) are of limited interest. Unfortunately, single-flash LiDARs capture the point cloud of the entire FOV within each frame, resulting in high power consumption.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"795 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123905532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter","authors":"Zhen Li, Zhiyuan Chen, M. Law, S. Du, Xu Cheng, Xiaoyang Zeng, Jun Han","doi":"10.1109/cicc57935.2023.10121219","DOIUrl":"https://doi.org/10.1109/cicc57935.2023.10121219","url":null,"abstract":"With the advent of the lnternet-of-Things (1oT) era, sensor nodes are required in almost all fields to achieve a better interaction between humans and the environment. Piezoelectric energy harvester (PEH), which exhibits an equivalent electrical model of an AC current source /P in parallel with the inherent capacitor CP, is a promising technology to resolve the energy problem of such sensor nodes. Recently, inductor-based rectifiers, capacitor-based rectifiers and hybrid rectifiers have been proposed to improve the energy extraction efficiency of PEH devices [1]–[5]. However, these structures all require the aid of additional capacitors or inductors to achieve bias-flip operation, as illustrated in Fig. 1. These extra passive devices are typically large, which can be a major bottleneck in system-volumeconstrained applications such as MEMS [4]. In response to the above problem, this work proposes a novel 8-phase self bias-flip PEH interface with charge recycling and reusing (SBFRR). By using the C P of 4 PEHs as flipping capacitors, this scheme achieves a high voltage flipping efficiency without using extra energy reservoirs. The 4 C P can also serve as flying capacitors to achieve switched-PEH DC-DC (SPDC) conversion for MPPT, while maintaining a MOPIR of >3.5× with a PEH input voltage (Vp) from 0. 78Vto4.9V.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116255889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}