2023 IEEE Custom Integrated Circuits Conference (CICC)最新文献

{"title":"An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ?S ADC with 105dB SFDR in 28-nm CMOS","authors":"Yi Zhong, Mingtao Zhan, Wei Wang, Xiyuan Tang, Lu Jie, Nan Sun","doi":"10.1109/CICC57935.2023.10121245","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121245","url":null,"abstract":"A low-power, small-area, and medium-to-high-resolution ADC is one of the critical building blocks in an SoC. lt is also a primary bottleneck of SoC time-to-market due to ful.lcustom design. The $mathrm{p}_{mathrm{i}}$ rior work of [1] addressed this issue by synthesizing a MASH ADC using augmented analog customized blocks. Although the design productivity is increased, the ADC performance is sacrificed, leading to only 58. 9dB SFDR and 9. 5b ENOB. Besides, the highly customized blocks such as opamp and comparator greatly restrict the design flexibility. An automated SAR ADC design by taking advantage of its inherent digital-friendliness is demonstrated in [2] –[4]. Nonetheless, the performance of these 3 works is still limited to 9. 5b ENOB. Also, a dedicated custom-made CDAC layout tool is demanded on top of the standard digital EDA tool, equivalently transferring circuit design effort to software development. A synthesized VCO-based $DeltaSigma$ ADC is proposed in [5]. However, this synthesis methodology cannot achieve high resolution due to the poor matching by automatic place and route (APR) and the low quantizer resolution. So far, none of prior synthesized ADCs has demonstrated over 69dB SNDR nor 75dB SFDR. Also, none of existing methodologies demonstrated synthesized ADCs for multiple specifications using one universal library.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125845416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Transceiver SoC for Wireless Indoor Sensing Data-fusion","authors":"Bufan Zhu, W. Deng, Ziwen Huang, Haikun Jia, Haiyang Jia, Angxiao Yan, Yumeng Yang, Junfeng Liu, Yu Fu, Shiyan Sun, Chao Tang, Taikun Ma, Jiajie Tang, B. Chi","doi":"10.1109/CICC57935.2023.10121231","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121231","url":null,"abstract":"Wireless indoor navigation/position system aims to navigate and localize a large number of people or objects inside buildings/places where GPS signals are unavailable. It requires both indoor position information and indoor environmental information. The indoor position information extraction can be performed by Ultra-wideband (UWB) sensors with high-precision positioning capability [1], [2], [3]. The indoor complex and diverse environment information can be obtained by using FMCW radar sensors. In addition, communication between devices/nodes is required to obtain environment information of various positions and enhance indoor navigation/position accuracy under NLOS environments through multi-source data-fusion. In order to support the wireless indoor sensing data-fusion, this paper introduces a digital-intensive 1T2R joint-radar-communication transceiver SoC. The transceiver consists of a UWB mode and an FMCW radar mode. The UWB mode of the transceiver is compatible with IEEE 802.15.4/4z, which can provide accurate ranging, position information, and communication capability. The FMCW radar mode can actively detect and model the indoor environment. It covers a wide frequency range from 6-to-11 GHz, which can support Channels 5 to 10 & Channels 11 to 14 according to the UWB protocol. The 1T2R structure supports a variety of UWB positioning/ranging algorithms, including two-way ranging, time-difference-of-arrival (TDoA), phase-difference-of arrival (PDoA), and angle-of-arrival. The UWB mode implements HRP PHY/MAC standards as described in IEEE 802.15.4/4z and supports data-rates of 0.85/6.81/27.24 Mb/s. In addition, in the FMCW mode, the transceiver can be configured as 1T1R or 1T2R, giving it the ability to provide accurate range results and a degree of angle results in a large range. As shown in the right part of the Fig. 1, the FMCW radar mode of the transceiver can cooperate between devices in the UWB mode to perform multi-device joint detection and modeling of the environment for multi-source data-fusion.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133374922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 1.6pJ/b 65Gb/s Si-Dielectric-Waveguide based Multi-Mode Multi-Drop sub-THz Interconnect in 65nm CMOS","authors":"Xuan Ding, Hai-xia Yu, Sajjad Sabbaghi, Q. Gu","doi":"10.1109/CICC57935.2023.10121251","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121251","url":null,"abstract":"Ever-increasing data generation and transmission demands have been driving great advancements in wireline communications from both electrical interconnect (E1) [1] and optical interconnect (O1) [2] for short- and long-distance scenarios, respectively. In the meter range, both El and Ol face great challenges: the lossy and bandwidth-limited channel is the bottleneck of El; For Ol, the features, such as the complex fabrication and high environment sensitivity, increase the power and cost budgets significantly, making it less economical for short-distance communications. To mitigate these issues, low-loss dielectric channel-based interconnects have been investigated and demonstrated [3] –[5]. However, they are all for point-to-point configurations, not suitable for multi-drop distributed architectures as shown in Fig.1. Thus, the unscalable feature limits their deployments. To address this important challenge, this paper adopts spatial multiplexers [6] and presents a Si dielectric waveguide (DWG) based multi-mode multi-drop sub-THz interconnect with great scalability for numerous ports and multi-dimensions. This approach is also more power and cost effective compared to Ol due to the elimination of exotic materials and devices, such as lasers and OE/EO, and sophisticated fabrications. lt only needs a low-cost and standard fabrication process with coarse alignment requirement.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115047339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 3.9kHz bandwidth and 2μV offset current sensor analog front-end with a capacitively coupled amplifier using a dual frequency conversion technique","authors":"S. Wada, Yoshikazu Furuta, S. Taniguchi, M. Kondo, S. Kawahara, T. Nezuka","doi":"10.1109/CICC57935.2023.10121229","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121229","url":null,"abstract":"Precision current measurement with low offset and low gain error is essential for battery management systems to perform accurate State-of-Charge (SOC) estimation in battery-powered vehicles. The simultaneous sampling of current and voltage enables measurement of battery capacity and/or battery impedance to estimate battery’s State-of-Health SOH or internal properties [1]. The bandwidth of the current sensor front-end is required to be on the order of kHz for those applications. The system-level chopping CHL technique [2] is proposed to improve an analog front-end (AFE) input offset while the reset of integrator is required each time the CHL operates, which limits the signal bandwidth. To overcome this bandwidth limitation, an AFE for a current sensor with a capacitively coupled amplifier (CCA) followed by a $2^{text {nd }}$-order $Delta Sigma$ modulator with correlated double sampling (CDS) and charge-preserving integration technique was proposed [3]. The CCA has a duty-cycled resistor to provide a DC bias to the o & input each time the polarity of the signal changes, and the operation causes the signal leakage, resulting in a AFE gain error. Moreover, an anti-aliasing filter (AAF) is required in automotive applications to attenuate unwanted noise as well as to protect the AFE from ESD noise. It also causes inherent gain errors due to voltage division by the impedance of the AAF and the CCA determined by the input capacitance of the CCA and sampling frequency. This paper proposes an analog front end for current sensors using a CCA with a dual frequency conversion technique in order to improve the CCA input impedance by reducing the operating frequency to half that of the $Delta Sigma$ modulator in the following stage. The proposed AFE shows $2 mu mathrm{V}$ offset and ± 0.2 % gain error with 3.9kHz bandwidth from $-50^{circ} mathrm{C}$ to $150^{circ} mathrm{C}$.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116375781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 12b 1GS/s ADC with Lightweight Input Buffer Distortion Background Calibration Achieving >75dB SFDR over PVT","authors":"Xianghui Pan, Buhui Rui, Yuefeng Cao, Yan Zhu, Chi-Hang Chan, R. Martins","doi":"10.1109/CICC57935.2023.10121262","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121262","url":null,"abstract":"With only an input-swing-comparable supply voltage, the ADC input buffer gives rise to a significant static distortion, inevitably calling for a large supply headroom for adequate linearity [1] [2]. A negative supply voltage is often necessary to maintain a proper input common mode voltage for the backend ADC that burdens the power management unit and induces reliability concerns. As an alternative, digital calibrations [3] [4] [5] are utilized to tackle the buffer’s impairments. While calibrating the dynamic distortion renders an excessive power/area cost with a constrained input [3] [4], the static distortion calibration is more reasonable. In [5], an auxiliary ADC is introduced as a reference for calibration, omitting the negative supply and showing a Nyquist SFDR of $sim$67dB in a 12b1GS/s ADC. However, the auxiliary ADC must reach adequate linearity, which is bulky and complex. The digital processing for correction is also costly [6]. This paper proposes a background input buffer calibration with a mild analog circuit overhead and the correction is on-chip in the analog domain, achieving < 76dB SFDR at Nyquist input.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122150003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 12-bit 1GS/s Current-Steering DAC with Paired Current Source Switching Background Mismatch Calibration","authors":"Chang-Un Park, Jae-Hyun Chung, S. Ryu","doi":"10.1109/CICC57935.2023.10121298","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121298","url":null,"abstract":"Current-steering DACs are known to be suitable for wideband applications owing to the fast current switching with differential switches and the low output load resistance [1] –[6]. In current-steering DACs, mismatches between the current sources(CS) are the major source of nonlinearity. To reduce the CS mismatch effect, previous works often utilized the Dynamic Element Matching (DEM) [1], [4] or current-source calibration techniques [2], [3], [5], [6]. The DEM randomizes the DAC switching to spread the mismatch tones as noise to improve the SFDR at the expense of increased noise floor, deteriorating the SNR. Background calibration techniques do not have the noise floor issue as they reduce the CS mismatch directly with PVT insensitivity. However, the periodic CS switching operations, disengaging for calibration and reengaging for normal operation, generate unwanted calibration spurs. These spurs can be also randomized as in [6], but the technique still has a disadvantage of increased noise floor near the calibration frequency.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125856357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 40nm 0.35V 25MHz Half-Select Disturb-Free Bitinterleaving 10T SRAM With Data-Aware Write-Path","authors":"Yifei Li, Jian Chen, Yuqi Wang, Zihan Yin, Hongyu Chen, Y. Ha","doi":"10.1109/CICC57935.2023.10121235","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121235","url":null,"abstract":"With the widespread applications of wireless sensors, implantable biomedical devices, and small handheld devices, the demand for ultra-low voltage SRAM is growing. However, the probability of soft errors at low voltages is also increasing, and using a bit-interleaving structure is essential for ultra-low voltage SRAM to mitigate soft errors efficiently. Nevertheless, the write half-select disturb, which results in unstable operation in the bit-interleaving structure, poses critical challenges to achieve faster writes at ultra-low voltages [1] –[5].","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129851619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 92 F2 / bit Physically Unclonable Function Exploiting Channel Charge Injection and Mismatch Accumulation","authors":"Injune Yeo, Dong-Woo Jee, J.-s. Seo","doi":"10.1109/CICC57935.2023.10121230","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121230","url":null,"abstract":"In the deployment of millions of edge devices connected via Internet of Things (loT), each of those devices are exposed as access points for security attacks. As a primitive solution to breaches, physical unclonable functions (PUF) are considered as one of the most cost/energy-efficient approaches providing hardware-oriented randomness, uniqueness, and reliability. PUF can be fundamentally classified into strong and weak PUFs. Strong PUFs can generate a large number of challenge-response pairs (CRPs) according to the given secret. However, due to the correlation between CRPs, it is vulnerable to attacks through the heuristic learning. On the other hand, weak PUFs typically produce a relatively small number of CRPs. Therefore, not only ideal uniqueness and stable response against voltage/temperature variations are important, but also efficient PUF cell area per bit ($left.mathrm{F}^{2} / mathrm{bit}right)$ is a critical metric for weak PUFs to produce a large number of CRPs with high density.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129665236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 21.8-41.6GHz Fractional-N Sub-Sampling PLL with Dividerless Unequal-REF-Delay Frequency-Locked Loop Achieving -246.9dB FoMj and -270.3dB FoMj,N","authors":"Wen Chen, Yiyang Shu, Xun Luo","doi":"10.1109/CICC57935.2023.10121208","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121208","url":null,"abstract":"To support millimeter-wave (mmW) multiple-band operations for the high-data-rate mobile wireless communication, the mmW PLLs with wide tuning range, low phase noise, and low power consumption are in great demand. As a key component of PLL, the mmW frequency dividers suffer from limited frequency range and consume the high power consumption [1] –[3]. Sub-sampling PLL (SSPLL) has become a popular candidate in mmW low-jitter frequency synthesis for its high phase detection gain and dividerless characteristic [4]. However, for a wideband SSPLL, a frequency-locked loop (FLL) based on divider is still demanded to ensure the correct locking frequency. Recently, FLL without divider is investigated [5]. Nevertheless, it has limited effective frequency correction range. This paper proposes a 21.8 to 41. 6GHz fractional-N SSPLL with dividerless unequal-REF-delay FLL (URD-FLL) in 40nm CMOS. Consuming only 680$cup$W, the URDFLL ensures that the PLL is correctly locked to the target frequency over a wide frequency range, without sacrificing the jitter performance. With a 100-MHz reference, the proposed PLL achieves 133. 3fs fractional-Njitter, -246.9dBFo$mathrm{M}_{mathrm{j}}$, and -270.3dBFo$mathrm{M}_{mathrm{j}mathrm{N}}$.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127257156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 1GS/s6-Core Programmable A/D Converter Array Supporting Architecture Restructuring and Multitasking","authors":"Zhishuai Zhang, Zijie Gao, Siyu Huang, Nan Sun, Lu Jie","doi":"10.1109/CICC57935.2023.10121311","DOIUrl":"https://doi.org/10.1109/CICC57935.2023.10121311","url":null,"abstract":"High-end mobile devices are desired to support multiple radio standards across a large bandwidth and DR span, e.g., from GSM, BLE, NB-loT to 5G and WiFi-6, which impose great challenges on the receiver’s ADC design. Deploying specialized ADCs for every standard is beneficial in performance and power efficiency, but will soon become too costly and bulky as the number of standards explodes. Multi-mode or reconfigurable ADCs are promising solutions, as they adapt to different standards (i.e., different BW and DR) with reasonable efficiency. However, most of the prior multimode ADCs (e.g., [1]) are based on circuit-level tuning or DSM loop configuring, thus providing a narrow performance range and limited standard coverage. Besides, these designs are usually exclusive between modes and cannot simultaneously support multiple standards.","PeriodicalId":108365,"journal":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129973341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}